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Cadence Chip Planning System 

Enterprise-class IC planning, estimation, and IP reuse

Chip Planning System enables early and accurate IC estimation, allowing tradeoffs among chip size, power consumption, cost, and time to market.

Cadence Chip Planning System Datasheet »

Product ImageDecisions made during the architectural planning stages of the IC design cycle largely determine the resulting size, power consumption, performance, and cost of a chip. Cadence® Chip Planning System helps electronics companies realize the biggest benefits by considering and quantifying a variety of architectural and IP reuse options early in the cycle. It provides a comprehensive environment that helps users plan IC designs, consider the reuse of internal or external intellectual property (IP), and accurately estimate key technical and economic metrics of a potential IC.

Since Cadence Chip Planning System is intuitive and easy-to-use, users need not be chip design experts to achieve expert results. A variety of organizations within an electronics company can use the system, from traditional IC designers and architects to technical marketing and field personnel, procurement and finance organizations, program and project management groups, and executive staff.

Chip Planning System includes a comprehensive IP catalog management system, creating a wholly contained intranet portal to accelerate collaboration and IP reuse within a global design organization. The system also integrates seamlessly into existing enterprise systems including commercial or internal IP catalogs, product lifecycle management (PLM) systems, and CAD environments.

A robust interface to EDA design and implementation technologies ensures that users can converge from initial estimation through final silicon. Chip Planning System directly interfaces into Encounter Digital Implementation System and other implementation solutions, enabling users to drive downstream convergence. The system is fully customizable, tunable, and programmable to deliver the utmost in estimation accuracy and enterprise integration.

  • Accurately estimates IC size, power, leakage, performance, and cost
  • Enables rapid what-if analysis across design architecture, IP, and manufacturing process options to optimize design specifications
  • Achieves die size and power reductions through architectural exploration
  • Generates complete IC economic analysis and budgetary quotes
  • Offers a fast, accurate, and easy-to-use environment across engineering, management, and sales and marketing organizations
  • Accelerates and promotes IP reuse through an included intranet-based IP catalog management system
  • Supports estimation with internal or custom IP and manufacturing processes
  • Supports estimations specific to leading foundry manufacturing processes
  • Enables pre-RTL power estimation, low-power planning, and CPF authoring and exploratio
  • Assesses performance achievability in specific manufacturing processes with specific IP components
  • Provides tunable estimation models for the utmost in estimation accuracy
  • Supports fully customizable IC economic models including key variables and equations
  • Programming API enables customized technical and economic analysis
  • Integrates with enterprise IP, PLM, and CAD environments
  • Enables convergence in silicon through direct interface to downstream design and implementation tools