Encounter RTL Compiler Public Endorsements 

• NEC Electronics
  NEC Electronics Tapes Out 10 40nm Designs of 20M Gates Using Encounter Digital Implementation Solution Including Synthesis
  
• AppliedMicro
  AppliedMicro Standardizes on Cadence Digital Design and Implementation
  
• SHHIC
  SHHIC Adopts Broad Range of Cadence Solutions for Advanced Semiconductor Design
  
• Tilera
  Tilera Utilizes Cadence Synthesis and Full Flow for High Performance Low Power Processors
  
• Global UniChip
  Global Unichip Selects Cadence Low Power Flow for DVFS Methodology
  
• STARC
  STARC Integrates Cadence Encounter Solution for Complex, Large-Scale Designs
  
• Toshiba
  Cadence Collaborates with Toshiba Corporation on Integrated Design Environment for COT and SoC Design
  
• Casio
  Casio Selects C-to-Silicon Compiler for High-Level Synthesis
  
• SiRF
  Cadence Low Power Solution Helps SiRF Balance Power and Performance
  
• Sequans
  Sequans Tapes Out 65nm Multi-Supply, Multi-Mode Mobile WiMax Chip with Cadence Low Power Solution
  
• UPEK
  UPEK Switches to Cadence for End-to-End Chip Design Flow
  
• Freescale
  Freescale Japan Tapes Out Chip with Multi-Supply and Power Shutoff Using Cadence Low Power Solution
  
• Moai
  Moai Improves Timing Closure and Reduces Test Data Volume and Application Time with RTL Compiler and Encounter Test
  
• Legend Silicon
  Legend Silicon Tapes Out Low Power 90nm Digital TV Chip and Selects Cadence as Primary EDA Partner
  
• Staccato
  Staccato Uses RTL Compiler and Cadence Low Power Solution to Reduce Power Consumption and Risk on 65nm UWB Chip
  
• SandLinks
  SandLinks Uses RTL Compiler to Predict and Optimize Power Consumption; CPF-Based Flow Saves 10 Weeks of Design Time
  
• Ricoh
  Ricoh Adopts Encounter Flow Based on Improved Efficiency and Turnaround Time from Top-Down Synthesis with RC-Physical
  
• NetEffect
  Cadence Helps NetEffect Improve Performance and Productivity
  
• Seiko
  Seiko NPC Sees Big Productivity Boost in DFT Flow With Integrated Cadence Test and Synthesis
  
• NEC Electronics Corp.
  NEC Electronics Corp. saw significant Design Cycle Time Reduction and Performance Improvement with optimized Leakage Power
  
• Symmid Semiconductor
  Customer Paper: RTL Compiler Physical Improves Predictability and Results for Symmid Semiconductor
  
• Texas Instruments
  Customer Paper: RTL Compiler Helps Texas Instruments Reduce Area and Speed Turnaround Time on
  WiMax SoC
  
• G2
  G2 Microsystems Improves Time-To-Market with Cadence Low Power Solution
  
• NEC Electronics America
  NEC Electronics America Uses RTL Compiler for 700 MHz, Low-power ARM11 Processor
  
• OmniVision
  Customer Interview: OmniVision Uses RTL Compiler for MSV, PSO, and Multi-Vt
  
• Atheros
  Atheros Tapes Out Industry's Highest Performance 802.11n Solution with RTL Compiler PLE
  
• Swati Design
  Swati Design Improves Area, Timing, and Power with RTL Compiler
  "Our client could only give us the synthesized gate level netlist. Area and low power are the biggest factors of concern, and there's an added restriction of using only high VT libraries. Using the N2N optimization alone, Encounter RTL Compiler is able to reduce the areas of 5 blocks of about 500K instances each by an average of 6%. These area savings are very significant in the multi million instance design, while improving the timing and power. One of the blocks was originally synthesized for 233 Mhz, and using Encounter RTL Compiler, we could achieve 255 Mhz using the netlist optimization alone. We are extremely happy with the support from Cadence to achieve these results. This ability to optimize an incoming netlist makes us more productive."
   
  Rao Pokala
  CEO, Swati Design
  
• Altek
  Altek Improves Chip Timing and Area with RTL Compiler
  
• Coolsand
  Coolsand Increases Designer Productivity and Reduces Chip Size with RTL Compiler
  
• ETRI
  ETRI Speeds Overall Design Turnaround Time with RTL Compiler
  
• Moai
  Moai Electronics Tapes Out Two USB Chips with RTL Compiler
  
• Centrality
  Centrality Reduces Chip Size and Shortens Design Cycle for GPS Chip
  
• Jennic
  Jennic Tapes Out Smaller and Lower Power ZigBee Controller
  
• Sandbridge
  Sandbridge Tapes Out with Cadence Low Power Flow
  
• Bay Microsystems
  Bay Microsystems Tapes Out High Performance Network Processor; Synthesizes 1.5M Instances Top-Down
  
• Magnum Semiconductor
  Magnum Semiconductor Sees 50% Runtime Reduction with RC 6.2 Release
  
• Sirific
  Sirific Wireless Speeds Time-to-Market for Two 3.5G RF Transceivers
  
• GUC
  GUC Improves ARM926 Frequency by 18% and Area by 10%
  
• Fujitsu
  Fujitsu Improves ARM9 Performance, Power, and Area with RTL Compiler and the Cadence Optimization Methodology kit for ARM Processors
  
• Comit Systems
  Comit Systems Expands Adoption of Cadence Front-end Technologies to Synthesis plus Test
  
• D2Audio
  D2Audio Tapes Out Smaller and Faster Chip in Less Time with RTL Compiler
  "Encounter RTL Compiler performed much better than our original synthesis tool with regards to synthesis times, area and timing reults. We have used Encounter RTL compiler to synthesize all blocks of our complex chip. We are very happy with the Cadence support at all levels in getting us productive. Rapid resolution of issues and high quality of technical support was a surprise and very welcome."
   
  Kevin Tomasek
  Hardware Design Engineer, D2Audio
  
• Hitachi
  Hitachi Communications Speeds Time-to-Market on 6 ASIC Tapeouts
  
• ST
  ST Speeds Time-to-Volume of HDTV Chip with Encounter RTL-to-GDSII Flow
  
• Fujitsu
  Fujitsu Tapes Out Over 150 ASICs with Encounter, Deploys RTL Compiler GXL For 65nm Reference Flow
  
• Intersymbol
  Intersymbol Adopts RTL Compiler To Speed Time-to-Market, Reduce Die Size, and Increase Frequency for Mixed-Signal Designs
  
• Faraday
  Faraday Completes Range of Low Power Tapeouts with Encounter
  
• Inphi
  Inphi Tapes Out 666 MHz Chip at 130nm Using RTL Compiler
  
• PA Semi
  PA Semi Tapes Out 65nm 2GHz Low Power Processor
  
• ATI
  Synthesis With PLE Produces Best Results After P&R At ATI
  
• Accent
  Top-Down MSV Enables Accent To Reduce Voltage and Meet Timing
  
• Toshiba America
  Toshiba America Achieves 2x Faster Runtime with Superthreading
  
• Vativ
  Retiming Enables Vativ To Reduce Pipeline Register Count By 45%
  
• Freescale
  Freescale Chooses Cadence as Primary EDA Vendor
  
• Cray
  Cray Tapes Out High Performance ASIC RTL Compiler DFT With Encounter Test
  
• Kawasaki Micro
  Kawasaki Micro Improves Area, Timing, and Power in Over 30 ASIC Tapeouts
  
• F5
  F5 Networks Saves 25% on Power and 12% on Area Using RTL Compiler
  
• Toshiba
  Toshiba Tapes Out First UniversalArray Chip, Using RTL Compiler Optimization to Speed Timing Closure
  
• S3
  Silicon & Software Systems Completes 65nm Consumer Chip with Cadence Encounter
  
• Comit
  Comit Speeds Time-To-Market, Improves Competitiveness
  
• Oki
  Oki Achieves Less Power and Smaller Area on ARM946-ES Core
  
• ITRI
  ITRI Achieves 40% Power Savings Using MSV and DVFS in Encounter Synthesis and Implementation
  
• Magnum
  Magnum Semiconductor Becomes the 100th Customer of RTL Compiler; Adopts Cadence Front-End Solution
  
• NVIDIA
  NVIDIA Uses RTL Compiler Extensively on GeForce7 Series Due to Performance and Area Benefits
  "In the highly competitive graphics processor market, NVIDIA stays ahead of the competition by developing high performance GPUs at aggressive cost points. We have used Encounter RTL Compiler synthesis extensively in developing the GeForce7 series GPUs because of its ability to generate a high quality netlist quickly which meets our aggressive timing and area targets."
   
  Brian Kelleher
  Senior Vice President of GPU Business Unit
  NVIDIA Corporation
  
• BroadLight
  BroadLight Closes Timing and Power on Network Processor Using Single-Pass Multi-Vt Optimization
  "BroadLight, the World Wide Leader of ITU-T PON components, develops the best-in-class and most cost-effective Passive Optical Network (PON) SoC's using Cadence's RTL Compiler synthesis. Encounter RTL Compiler's single-pass multi-vt optimization enabled us to meet our network processor's challenging timing requirements while keeping power consumption in control."
   
  Igor Elkanovich
  Director of VLSI
  BroadLight
  
• Siano
  Siano Speeds Power and Timing Closure on Mobile Digital TV Chip
  "Developing silicon receivers for mobile digital television poses many design challenges, and Encounter RTL Compiler helped us meet those challenges. Controlling power consumption is important to us, and Encounter RTL Compiler's single pass multiple voltage threshold optimization and clock gating enabled us to meet our power constraints while still achieving our timing target. Encounter RTL Compiler's ability to synthesize mixed Verilog and VHDL top-down with fast runtimes and a smooth flow into gate-level verification helped us meet our schedule while developing the IP necessary to support multiple standards."
   
  Vice President of R&D
  Siano Mobile Silicon
  
• TransChip
  TransChip Enhances CMOS Imaging Chip Performance
  "RTL Compiler's optimization helped TransChip to close timing at a faster final design frequency with the same area after place & route. The tool runtime for this design was under two hours for 400,000 gates, and significantly shorter when compared to previous front-end/back-end iteration procedures, which took days. RTL Compiler is an essential component in TransChip's CAD flow, helping us to close timing faster on complex designs, making our products more competitive."
   
  Eli Assoolin
  Physical Design and CAD Manager
  TransChip
  
• Wavion
  Wavion Reduces Datapath Area by 15% on Wireless Networking Chip
  "As a world leading developer of wireless networking systems, our designs are very datapath heavy, yet we also need to keep our die sizes small. Encounter RTL Compiler enabled us to reduce area in our datapath logic by up to 15% over traditional synthesis architectures. Its top-down global synthesis automatically optimized the datapath and control logic together to deliver this smaller area while still meeting our performance goals. All in all, we could not have met our area targets without the use of Encounter RTL Compiler."
   
  Nir Yona
  VP of R&D
  Wavion Networks, Ltd.
  
• Wintegra
  Wintegra Speeds Network Processor by 13% While Saving Area, Power, and Engineering Resources
  As a designer of single chip solution for the access networks, we have to balance many demands - high complexity, high performance, smaller die size, all while meeting our power budget. Encounter RTL Compiler's global synthesis allows us to run synthesis on larger blocks, thus saving area, power, and engineering resources. Perhaps most importantly, it created a netlist that converged to 13% better timing. In our chips, frequency improvements translate directly to performance improvements. RTL Compiler's ability to produce a faster chip gives us a better chance to win more markets and use our NPU in more applications.
   
  Yoram Yeivin
  Wintegra, Ltd.
  
• Sunplus
  Sunplus Saves Cost Through Reduced Die Size On DVD Chip And Speeds Time To Market
  
• Global UniChip
  Global UniChip Improves Quality of Silicon with Cadence Synthesis Technology
  
• Accent
  Accent Reduces Power by 40% With Encounter Low Power and MSV Implementation
  
• Canon
  Canon Adopts RTL Compiler For Faster Time to Better QoS and Requires ASIC Vendors to Support It
  
• Epson
  Epson Doubles Productivity in LCD Controller Chip Tapeout
  
• Nethra
  Nethra Speeds Tapeout of Image Processor
  
• Essence
  Essence Reduces Synthesizable Area by 30 Percent
  
• Ricoh
  Ricoh Tapes Out 90nm Chip Early using RTL Compiler
  
• Wipro Technologies
  Wipro Technologies Adopts Cadence Design Systems for Nanometer Designs
  
• Sanyo
  Sanyo Improves Speed, Power, Area on Digital Consumer Product
  
• Oki
  Oki Tapes Out with 45% Power Reduction and 12% Area Reduction
  
• Azul
  Azul Implements High-Speed Network-Attached Processor
  
• Chelsio
  Encounter RTL Compiler Outperforms Design Compiler at Chelsio
  
• ATI
  ATI Improves Timing and Reduces Chip Area with Shorter Design Cycle Times
  
• Procket Networks
  Procket Networks Standardizes on Encounter RTL Compiler for its Synthesis Tool of Choice
  
• TeraBlaze
  TeraBlaze Closes Timing Faster with Smaller Area on High Speed Networking Design
  
• nVidia
  nVidia Deploys Encounter RTL Compiler in Production
  

Foundries

• TSMC Reference Flow 10.0
  Cadence Delivers 28-Nanometer Design Capabilities for TSMC Reference Flow 10.0
  
• UMC
  UMC Adopts Cadence Reference Flow for 40nm Design
• SMIC
  SMIC and Cadence Announce 65nm Low Power Reference Flow
  
• TSMC
  Cadence and TSMC Announce CPF-Based Reference Flow 9.0
  
• TSMC Reference Flow 8.0
  Cadence Accelerates 45-nm Design With TSMC Reference Flow 8.0
  
• TSMC Reference Flow 7.0
  Cadence and TSMC Collaborate to Accelerate 65-Nanometer Design with Reference Flow 7.0
  
• IBM, Chartered, Samsung, Artisan
  Cadence, Common Platform, and ARM Physical IP Deliver 45-nm Low Power Reference Flow
  
• IBM, Chartered, Samsung
  Cadence, IBM, Samsung and Chartered Deliver 65NM Reference Flow
  
• IBM, Chartered
  Cadence, IBM, Chartered Deliver 90nm Low Power Yield-Aware Flow
  
• UMC
  Cadence and UMC Deliver CPF-Based Low Power Reference Design Flow
  
• UMC
  UMC Releases Comprehensive Low Power Reference Design Flow Package
  
• Dongbu Electronics
  Dongbu Electronics Adds RTL Compiler To Its Reference Flow
  
• SMIC
  SMIC and Cadence Deliver 90nm Low Power SoC Solution
  

IP Vendors

• ARC
  ARC Processors Support RTL Compiler Synthesis
  
• ARM
  Encounter RTL Compiler Supported in Reference Methodology for ARM Cortex-A9 Processor
  Encounter RTL Compiler Supported in Reference Methodology for ARM11 MPCore and ARM1176JZF-S Processor
  ARM Cortex-R4 Reference Methodology Supports RTL Compiler
  ARM Cortex-A8 High Performance Low Power Processor Design Flow Uses RTL Compiler
  ARM and Cadence Deliver Methodology Kit to Improve Performance, Power, and Area of Synthesizable Cores
  Cadence and ARM Upgrade Quality of Silicon Results for ARM Partners with RTL Compiler Synthesis
  
• Artisan
  RTL Compiler Delivers Excellent Performance and Area Results on Artisan Libraries
  Accent, ARM and Cadence Collaborate to Improve Low-Power Design
  
• Denali
  Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology
  Denali Announces Databahn Support for RTL Compiler, Achieving Smaller, Faster, and Lower Power Results
  
• Faraday
  Faraday Libraries and Memories Integrated into UMC-Cadence Reference Flow
• IBM
  Custom-Synthesized Design Approach Reduces Time-To-Market for PowerPC Designers
• MIPS Technologies
  Cadence and MIPS Technologies Deliver Encounter Reference Methodology for Industry's Highest
  Performance 32-bit Core Family
• PalmChip
  PalmChip Qualifies Cadence Encounter Synthesis for AcurX SoC Platform
• Tensilica
  Tensilica Enhances Reference Flow With Cadence Encounter RTL Compiler
  Tensilica Adds Encounter RTL-GDSII Support for Diamond Standard Processor Cores
  
• Virage Logic
  Virage Logic and Cadence Further Enable Low-Power Design
  

ASIC Vendors

• Agere Systems
  Agere Systems Uses Cadence Encounter RTL Compiler Synthesis for ASIC Customers
  
• Fujitsu
  Fujitsu Supports RTL Compiler for ASIC Handoff
  
• IBM
  IBM ASIC 65nm Kit Supports RTL Compiler and Encounter Test
  IBM Qualifies Encounter RTL Compiler for ASIC Design Flow
  
• K-MICRO
  Kawasaki Micro Encourages ASIC Customers to Use RTL Compiler; Accepts Netlist Handoff
  
• NEC
  NEC Adopts RTL Compiler and Supports it for ASIC Handoff
  
• Renesas
  Renesas Customers Can Achieve Timing, Area, Power Advantages at 90nm and Below
  
• ST
  ST Micro Supports RTL Compiler After Reducing Chip Area in Tapeouts
  
• Texas Instruments
  TI Supports RTL Compiler Netlists for 130nm, 90nm, and 65nm Standard Cell ASIC
  
• Toshiba
  Toshiba Supports Cadence Encounter RTL Compiler for ASIC Design Flow
  

• EETimes
  RTL Compiler Wins EETimes "Best Synthesis Tool" Poll
  
• LSI
  Encounter RTL Compiler GXL Wins Japan’s "LSI of the Year" Award
  
• GeneSys
  GeneSys Supports RTL Compiler Due To High Demand for Better QoS on 90nm Designs
  
• IEC
  Cadence First Encounter Global Physical Synthesis Wins 2005 IEC DesignVision Award
  
• Intel
  Cadence® Encounter™ Platform Now Available on 64-Bit Intel® Xeon™ Processor-Based Systems
  
• Silicon Design Chain
  Silicon Design Chain Validates Enhanced Power Management Techniques to Cut Leakage Power by 98.5%
  Silicon Design Chain Collaboration Demonstrates Significant 90-nanometer Total Power reduction
  
• STARC
  Cadence Delivers 50% Power Savings in Latest STARC Production Flow