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Logic Design
Chip planning
Decisions made during the architectural phase of the IC design cycle have a major impact on the ultimate size, power consumption, performance, and cost of the final chip. Cadence
®
chip planning solutions enable design teams to balance these often conflicting goals by performing rapid what-if analysis and optimizing design specifications to achieve an optimal chip plan.
Cadence InCyte Chip Estimator
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost. Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
Learn more
»
Cadence Chip Planning System
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy. Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
Learn more
»
Constraint design and validation
Timing constraints drive optimization and measurement of a chip toward its most critical project goals, yet constraint design remains a mostly manual and error-prone process. The Cadence
®
solution automates constraint design, validation, and exception generation to improve design productivity and quality, and ensures that the silicon functions as intended.
Encounter Conformal Constraint Designer
Automates the generation, validation, and refinement of constraints to ensure that timing constraints are valid throughout the entire design process, helping designers achieve rapid timing closure.
Learn more
»
Logic synthesis
Creating the best balance of performance, power, and area from a given RTL has become an increasingly complex task—especially given the many implementation options coupled with uncertainties surrounding the effects of physical interconnect. Cadence
®
global logic synthesis delivers new algorithms and approaches to automate the complex tradeoff process involved in achieving these multiple and sometimes conflicting goals.
Encounter RTL Compiler
Allows engineers to concurrently optimize timing, area, power, and signal integrity. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation.
Learn more
»
Encounter RTL Compiler with Physical
Enables logic designers to account for physical interconnect—-without the need to learn how to do physical design.
Learn more
»
Equivalence checking
Design teams must ensure their RTL functions according to specification, while coping with the myriad complex transformations that the RTL undergoes along the path to silicon. Equivalence checking employs formal methods to exhaustively verify that a transformed netlist is functionally equivalent to the golden RTL or netlist. Cadence
®
equivalence checking technology works completely independent of implementation algorithms, eliminating false positives or missed bugs that can make it into the implemented chip.
Encounter Conformal Equivalence Checker
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Low-power validation
Implementing aggressive power reduction techniques affects the functionality of a design and causes logic and structural transformations during implementation. Cadence
®
low-power validation technology delivers early validation of the power specification using the production-proven Common Power Format (CPF) while ensuring proper implementation of power-saving logic and structures throughout the flow.
Encounter Conformal Low Power
Combines equivalence checking and low-power functional checks to enable full-chip verification of designs that consume less power.
Learn more
»
Engineering change order
Whether it’s adding or removing logic in a design or cleaning up routing for signal integrity, engineering change orders (ECOs) can be a risky and time-consuming manual process. Even if the change is implemented in the netlist, there might not be enough spare gates on the mask to physically implement it. Cadence
®
technology combines automatic ECO analysis and design netlist modification with world-class equivalence checking, allowing designers to implement ECOs for pre- and post-mask layout. With upfront knowledge of whether correct implementation is achievable, design teams can change plans and target workable solutions to stay on schedule.
Encounter Conformal ECO Designer
Combines automatic ECO analysis and design netlist modification with world-class equivalence checking. Brings automation and predictability to the ECO process.
Learn more
»
Test
Exploding design complexity combined with increasing parametric process variations and the need for test-mode power management techniques make it challenging to create test vectors that meet stringent quality requirements for nanoscale silicon. Cadence® Encounter® DFT Architect and Encounter True-Time ATPG technologies optimize test coverage and product quality while reducing development costs and schedules. A single logic + DFT synthesis engine and environment optimizes area, timing, and power to deliver the highest quality netlist for both physical implementation and ATPG flows.
Encounter DFT Architect
Helps design teams minimize cost of test with a flexible compression solution combined with a power-aware, unified methodology for specifying, inserting, and verifying full-chip tests.
Learn more
»
Encounter True-Time ATPG
Provides defect-based modeling capability with patented pattern fault technology–—the basis for gate-exhaustive fault testing. Supports stuck-at and transition fault models. Provides power-aware ATPG and timing-aware ATPG for small delay defects.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Static timing analysis
Performing static timing analysis on today’s chips—where physical interconnect dominates the delay equation—requires a way for logic designers to account for physical effects without having to learn physical design. Cadence
®
static timing analysis increases productivity and accuracy by incorporating this data in a powerful logic-design–oriented use model and analysis environment.
Encounter Timing System
Serves both front-end logic designers looking for high-quality static timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff.
Learn more
»
Formal analysis
Cutting design and verification time while improving product quality requires a formal means of verifying RTL functional correctness with assertions that bypasses the need for testbench simulation. Cadence
®
formal analysis technology puts design teams months ahead of testbench simulation by supporting an assertion-based methodology and delivering fast and predictable RTL block bring-up without test vectors.
Incisive Formal Verifier
Performs formal analysis in the assertion-based verification and debug of RTL block designs, before testbench availability, to speed design convergence.
Learn more
»
Testbench simulation
Verification often creates a bottleneck in delivering today's highly integrated electronic systems and chips. Cadence
®
testbench simulation solutions simplify and speed verification—from individual blocks to the full chip and all the way to the project level—by combining leading-edge process automation with the comprehensive Plan-to-Closure Methodology.
Incisive Design Team Simulator
Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (code, functional, transactional) and HDL analysis capabilities.
Learn more
»
Design and verification IP modeling
To maximize design predictability and quality, engineers need reusable verification IP that spans block to chip to system levels and derivative projects. Cadence
®
Verification IP (VIP) automates and speeds compliance verification for advanced communication protocols, provides metric-based data to interpret and report simulation results, and supports all IEEE-standard languages.
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification.
Learn more
»
Verification management
Achieving a predictable path to verification closure requires automated planning and metrics management with comprehensive coverage at block, chip, and system levels. Cadence
®
technology tracks the progress of an evolving design against its functional, performance, and schedule objectives simultaneously. It automates the deployment of simulation runs, analyzes failures and coverage data, and guides the steps toward closure.
Incisive Desktop Manager
Automates and guides the everyday deployment and visualization of verification tasks and results.
Learn more
»
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification.
Learn more
»
Cadence Chip Planning System
An enterprise-class IC planning and IP reuse environment designed for larger, global organizations needing the utmost in technical and economic estimation accuracy. Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system.
Learn more
»
Cadence InCyte Chip Estimator
Enables accurate estimation of IC size, power consumption, leakage, performance achievability, and cost. Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Encounter Conformal Constraint Designer
Automates the generation, validation, and refinement of constraints to ensure that timing constraints are valid throughout the entire design process, helping designers achieve rapid timing closure.
Learn more
»
Encounter Conformal ECO Designer
Combines automatic ECO analysis and design netlist modification with world-class equivalence checking. Brings automation and predictability to the ECO process.
Learn more
»
Encounter Conformal Equivalence Checker
Handles complex datapath, digital custom logic, custom memories, and FPGA designs—from RTL to layout. Performs functional checks to verify clock synchronization.
Learn more
»
Encounter Conformal Low Power
Combines equivalence checking and low-power functional checks to enable full-chip verification of designs that consume less power.
Learn more
»
Encounter DFT Architect
Helps design teams minimize cost of test with a flexible compression solution combined with a power-aware, unified methodology for specifying, inserting, and verifying full-chip tests.
Learn more
»
Encounter RTL Compiler
Allows engineers to concurrently optimize timing, area, power, and signal integrity. Offers a unique set of patented global-focus algorithms and physically-aware layout estimation.
Learn more
»
Encounter RTL Compiler with Physical
Enables logic designers to account for physical interconnect—-without the need to learn how to do physical design.
Learn more
»
Encounter Timing System
Serves both front-end logic designers looking for high-quality static timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff.
Learn more
»
Encounter True-Time ATPG
Provides defect-based modeling capability with patented pattern fault technology–—the basis for gate-exhaustive fault testing. Supports stuck-at and transition fault models. Provides power-aware ATPG and timing-aware ATPG for small delay defects.
Learn more
»
Incisive Design Team Simulator
Supports full multi-language simulation including SystemVerilog. Provides comprehensive coverage (code, functional, transactional) and HDL analysis capabilities.
Learn more
»
Incisive Desktop Manager
Automates and guides the everyday deployment and visualization of verification tasks and results.
Learn more
»
Incisive Formal Verifier
Performs formal analysis in the assertion-based verification and debug of RTL block designs, before testbench availability, to speed design convergence.
Learn more
»
Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification.
Learn more
»
Content Query Web Part [1]
White paper: Eliminating Routing Congestion Issues with Logic Synthesis
Archived webinar - Understanding Impact of Implementation Choices, Linking Back to Original IC Design Goals
speakTECH Feeder Viewer for Community Server
Recent Blog Posts
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RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!
My Wish List For The New Decade
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