Home > Products > Logic Design > Resource Library

Share

  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Logic Design  

77 resources found
 
Title Type Rated
Clock Concurrent Optimization Technical Paper
Date: 27 Jan 2012
Technical Paper
 0
Recommend!
Encounter DFT Architect Datasheet
Format: .PDF    Date: 14 Dec 2011
Datasheet
 6
Recommend!
Encounter True-Time ATPG Datasheet
Format: .PDF    Date: 14 Dec 2011
Datasheet
 13
Recommend!
Encounter Diagnostics Datasheet
Format: .PDF (1.1MB)    Date: 14 Dec 2011
Datasheet
 7
Recommend!
Encounter Conformal Constraint Designer Datasheet
Format: .PDF    Date: 01 Nov 2011
Datasheet
 8
Recommend!
Cadence DFM services Datasheet
Format: .PDF (1.5MB)    Date: 11 Oct 2011
Datasheet
 9
Recommend!
Encounter Conformal ECO Designer Datasheet
Format: .PDF    Date: 01 Sep 2011
Datasheet
 12
Recommend!
Encounter Conformal Low Power Datasheet
Format: .PDF    Date: 31 Mar 2011
Datasheet
 6
Recommend!
Encounter RTL Compiler Datasheet
Format: .PDF    Date: 04 Feb 2011
Datasheet
 9
Recommend!
Encounter RTL Compiler with Physical Datasheet
Format: .PDF    Date: 04 Feb 2011
Datasheet
 10
Recommend!
Encounter Timing System Datasheet
Format: .PDF (1.6MB)    Date: 28 Jan 2011
Datasheet
 12
Recommend!
Practical application of high-level synthesis in SoC designs on-demand webinar
Date: 08 Dec 2010
Webinar
 2
Recommend!
3D ICs with TSVs—Design Challenges and Requirements White Paper
Format: .PDF    Date: 06 Dec 2010
White Paper
 7
Recommend!
Encounter Conformal Equivalence Checker Datasheet
Format: .PDF    Date: 29 Nov 2010
Datasheet
 2
Recommend!
EDA360: The Way Forward for Electronic Design
Date: 27 Apr 2010
Other
 4
Recommend!
Cadence NewsLink - Issue 5
Date: 28 Sep 2009
Newsletter
 1
Recommend!
Cadence Chip Planning System Datasheet
Format: .PDF    Date: 25 Sep 2009
Datasheet
 7
Recommend!
Archived webinar - How Logic Designers Can Avoid Congestion Nightmares
Date: 24 Sep 2009
Webinar
 0
Recommend!
Logic Design Webinar Series
Date: 17 Sep 2009
Webinar
 1
Recommend!
Cadence InCyte Chip Estimator Datasheet
Format: .PDF    Date: 10 Sep 2009
Datasheet
 3
Recommend!