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Logic Design 

Press Releases
Cadence and TSMC Strengthen Collaboration on Design Infrastructure for 16nm FinFET Process Technology
ARM and Cadence Partner to Implement Industry’s First Cortex-A57 64-bit Processor on TSMC 16nm FinFET Process
Cadence Encounter RTL-to-GDSII Flow Enables Sharp to Achieve 2X Improvement in Turnaround Time

Cadence tools tape out 20-nm SoC test chip for ST
Cadence has design flow for SMIC 40nm process
DesignCon 2011 Videos: New 3D-IC Design Offering, Rahul Deokar, Cadence

CDNLive Korea 2014
07/15/2014 - Lotte Hotel World, Seoul, Korea
CDNLive India 2014
08/12/2014 - Bangalore, India

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