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Logic Design

Cray Inc

Design Challenge
	Create a 4-million gate ASIC on a nine-month design schedule to meet critical market window
	Integrate legacy components into new design
	Find a vendor to address the physical design and complete DFT
Cadence Solution
	Partnered with Cray to complete the physical design and address the DFT challenge
Read Full story »

F5 Networks Inc

Design Challenge
	Design an ASIC that was approximately four times larger than previous designs in both silicon area and gate count
	Apply new methodology to deal with challenges brought on by increased design size and complexity
Cadence Solution
	Implemented Cadence Encounter® RTL Compiler global synthesis
Read Full story »

Fujitsu Microelectronics

Design Challenge
	Align power design around CPF with accurate simulation
	Move to smaller geometries
	Reduce design time and improve QoS
Cadence Solution
	Integrated, proven design solution leverages success in new applications
	Accurate verification of final design improves silicon
Read Full story»

Inphi Corporation

Design Challenge
	Achieve 666 MHz in a complex 130-nm mixed-signal design
	Adopt a solution to overcome challenges in floorplanning and routing
Cadence Solution
	Enabled accelerated turnaround time in the design using Cadence® Encounter® RTL Compiler global synthesis
	Automatic RDL routing using SoC Encounter flip-chip router helped team meet schedule
Read Full story »

NEC video Martin Spohr NEC video Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.

nVidia Bruce Cory nVidia Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.

NVIDIA Chris Malachowsky NVIDIA Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.

P.A. Semi Amit Chandra P.A. Semi Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.

P.A. Semi Dan Dobberpuhl P.A. Semi Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.

Sound Design

Design Challenge
	Develop the industry’s first monolithic, 4-core audio aid
	Shrink the die size to meet a 3.8mm limit for the human ear
	Meet ultra-low power targets with customized clock timing and advanced chip stacking
Cadence Solution
	Provide a complete, production-proven, advanced digital design, implementation, and verification flow
	Mitigate risk and optimize time to productivity with expert design consulting services
Read Full story»

TeraBlaze

Design Challenge
	Create a scalable data switch fabric with full-duplexed bandwidth of over 200 Gb/sec in TSMC 0.13µ
	Improve turnaround time with a new design flow that would allow the team to explore hardware architectures up front in the design
Cadence Solution
	Provided the Encounter™ RTL Compiler synthesis solution
	Met all timing closure challenges and improved area results
Read Full story »

TSMC North America David Lan TSMC David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.

Via Telecom

Design Challenge
	Adopt an equivalency checking solution to enable them to run RTL to netlist comparisons at the chip level
	Find a solution that includes the ability to check clock domain crossings
Cadence Solution
	Deployed Encounter® Conformal® Equivalence Checker (EC) to address both the verification and clock domain checking challenges
Read Full story »

ZMD Thilo von Selchow ZMD Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.

Freescale Semiconductor

Anis Jarrar
Freescale Semiconductor
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.