F5 Networks Inc
Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.
Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.
Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.
Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.
Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.
TSMC North America
David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.
Thilo von Selchow
Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.