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Cadence Low-Power Methodology Kit

Overview document

Meeting the power consumption and density requirements of today's electronics devices means power must be considered at all stages of the design process—from architecture through implementation. If not done properly, adding advanced power management techniques to an already complex design process, can significantly increase project costs and risks. The Cadence Low-Power Methodology Kit enables design and implementation teams to streamline the adoption of low-power techniques, optimize their usage, and get predictable results while also minimizing risks.

The Cadence Low-Power Methodology Kit provides users with a complete front-to-back methodology for low-power implementation and verification. It combines industry-leading Cadence low-power technology from the Incisive and Encounter platforms with a single power specification format (CPF) and proven power management methodologies.

More than just a methodology, the kit captures best practices in the form of executable flows, as well as detailed checklists that ensure a high level of automation and clean handoffs between different tasks and groups within the design team. Additionally, the kit is highly modular, allowing companies to adopt the technology incrementally and focus only on what are the most critical for their designs.

Key benefits



Enables teams with limited experience with advanced low-power techniques to adopt them in their designs with significantly reduced risk
Provides significant productivity improvements through supplied infrastructure
Restores schedule predictability through application of proven processes
Avoids common problems in low-power design through expert knowledge and best practices
Optimizes flows and tradeoff analysis to ensure technology is applied in ways that give the best results and improve overall quality of silicon
Reduces overall packaging and system cost by allowing for expanded application of low-power techniques


Cadence Low-Power Methodology Kit


Kit Contents



The Cadence Low-Power Methodology Kit includes the following;
Wireless segment representative design (SRD) including all required views for RTL design, physical implementation, and verification (including testbench)
Detailed low-power methodology guide covering all aspects of low-power implementation
Reference flow implementations with step-by-step walkthroughs
Detailed documentation of the SRD and reference flow
Detailed flow checklists, and trade-off analysis
Expert consulting designed to map the verified and demonstrated methodologies to a specific customer design


SiP Leadership Continues
What's new

Cadence SoC Functional Verification Kit
This new Kit offers design and verification teams a comprehensive solution to ease the adoption of new verification technologies and methodologies.

New! SoC Functional Verification Kit Demo
This demo highlights the SoC Functional Verification Kit and how functional verification methodologies go beyond basic tools.

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