Cadence Kits
Cadence SoC Functional Verification Kit
Cadence Low-Power Methodology Kit
Cadence RF SiP Methodology Kit
Cadence AMS Methodology Kit
Cadence RF Design Methodology Kit
Incisive functional verification
Encounter digital IC design
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
IP catalog
Print-friendly version
Cadence AMS Methodology Kit

Overview document

The Cadence® AMS Methodology Kit addresses analog/mixed-signal design challenges across some of today's most competitive markets, including wireless, wired networking, and personal entertainment electronics. The Kit delivers a verified methodology, enabling IP, and consulting, all of which is demonstrated on an end-to-end mixed-signal design example.

The Cadence AMS Methodology Kit is based on the Cadence Advanced Custom Design methodology. This methodology executes a "meet in the middle" design approach that achieves an optimum balance between the needs for speed and silicon accuracy.

Key benefits



Establishes a design process that allows teams to work with the analog mixed-signal content in the context of the complete design through upfront simulation and physical design planning
Allows effective use of parasitic data through first-cut route and top-level parasitic extraction evolving to block-level and targeted post-layout re-simulation
Enables reuse and migration of analog mixed-signal blocks through a repeatable block creation method
Lets designers manage multiple power supplies through top-down methodology for defining voltage supplies


The Kit executes to a prescribed methodology



Advanced Custom Design Methodology Download PDF


AMS Kit key functional areas, scenarios and modules



1.Methodology Overview
2.Environment Infrastructure
3.Design Partitioning
4.Design Concept Validation
5.Constraint-driven IP Create & Re-use
6.Block IP Yield Optimization
7.Block IP Characterization
8.External Block IP Import
9.Design Floorplanning
10.Design Performance Validation
11.Digital Block Authoring and Inter-operability
12.Design Physical Assembly
13.Design Physical Verification
14.Post-layout Design Sign-off Functional Validation
15.Design IP Publishing for Re-use

Facilitate top-down development in context of the entire design (Top-down functional verification Flow) Download PDF
Enable IP block reuse and migration (AMS block IP creation and re-use Flow) Download PDF
Incorporate digital implementation in the context of analog with an Analog-driven (Top-down physical design Flow) Download PDF


Components of the Cadence AMS Methodology Kit


SiP Leadership Continues
What's new

Cadence SoC Functional Verification Kit
This new Kit offers design and verification teams a comprehensive solution to ease the adoption of new verification technologies and methodologies.

New! SoC Functional Verification Kit Demo
This demo highlights the SoC Functional Verification Kit and how functional verification methodologies go beyond basic tools.

Resource library
 

Overview documents
White papers
News and events

Support and services
 

Engineering services
SourceLink
Education
Downloads

Request Information

Virtuoso eNewsletter