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Home > Products > Cadence Kits > Cadence RF Design Methodology Kit
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Cadence RF Design Methodology Kit
The Cadence RF Design Methodology Kit helps shorten product development cycle time by increasing silicon predictability and enabling greater RF design productivity. This includes demonstrating advanced methodologies for intelligently managing RLCK parasitics, inductor synthesis and modeling, full-chip verification through a new "local" envelope technique, PLL simulation guide. It also links system-level design with IC design. The Kit further incorporates methodologies that enable designers to accurately, yet rapidly verify complete designs that include system-level digital, analog base-band, and RF circuitry.
The RF Design Methodology Kit is based on an 802.11b/g CMOS WLAN reference design, which uses IP from Helic S.A. Athens, Greece. The segment representative design focuses on simplifying challenges associated with the RF transceiver and analog portion of the baseband circuitry. Fully extracted RLCK views ensure silicon predictability by accurately verifying the chip at the circuit level and upper levels with detailed parasitic information. Intelligent RC reduction and simulation strategies further ensure rapid simulation results. Re-usable, pre-setup components include test benches, models, and simulation plans for blocks such as LNA, PLL, down conversion mixers, Rx/TX band pass filters, and power amplifiers. These allow designers to fully and quickly leverage the fast, silicon accurate design capabilities of the Cadence Virtuoso custom design platform.
Key benefits
 | Silicon predictability — reduce unplanned re-spins
| |  | Verification of wireless IC design within system-level context | | Full-chip functional verification methodology | | Development & validation of FVM (functional verification model) with embedded assertions | | Simultaneous verification of the RF, analog, digital, and system domain | | Effective use and management of parasitic data | | Analyzing noise distribution and quickly prototyping of noise isolation schemes | | Seamless top-down and bottom-up design processes |
| | Faster turn-around time
| | | Prescribed advanced methodology (documented and demonstrated on an 802.11 b/g WLAN reference design) | | PLL simulation guide | | New technology to accurately model & characterize PLL at the transistor level | | Using Perturbation Projection Vector (PPV) method to significantly speed up top-level simulation | | Reusable components from the reference design including test benches, simulation plans, models | | Methodologies around the latest verification technologies for a rigorous, repeatable, and optimized design process | | Inductor synthesis provides the rapid implementation and modeling of inductors early in the design process | | Intelligent management of complete RLCK extracted views for rapid, yet highly accurate simulations at the chip level | | Leverages system-level view across digital, analog, and RF domains for a more complete, accurate verification of design |
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The Kit combines platform flows and methodologies that
| Components of the Cadence RF Design Methodology Kit |
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Kit Contents
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802.11 b/g CMOS WLAN reference from Helic design, including RX, TX, and AMS blocks at behavioral level
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Complete 802.11 b/g test benches at both the block and chip level
| | | Complete behavioral models, transistor-level schematics, and layout for the segment representative design | | Detailed step-by-step documentation to enable users to verify/validate the overall flow enabled by enhanced hands-on-workshops | | Proven and validated RF IC and System IC methodologies | | Pin-accurate behavioral and silicon accurate calibrated models | | Re-usable, pre-setup components including test benches, models, and simulation plans for all RF transceiver blocks | | Noise modeling for System-level simulation | | Applicability consulting designed to map the verified and demonstrated methodologies to a specific customer design |
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Applicability consulting designed to map the verified and demonstrated methodologies to a specific customer design
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