Cadence Design Systems, Inc.
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PRODUCTS
Cadence Kits
Incisive functional verification
Encounter digital IC design
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
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SOLUTIONS
Advanced node design
Low power
Logic design
Advanced verification
Digital implementation
Custom design
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SERVICES
Incisive functional verification
Encounter digital IC design
Virtuoso custom IC design
Allegro IC-PKG-PCB co-design
PCI Express vertical solution
Ethernet vertical solution
Low-power design services
PowerPC design services
Silicon engineering
European start-up accelerator
Working with us
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ALLIANCES
Verification Alliance program
Power Forward Initiative
Foundry program
OpenChoice program
Connections program
Channel partner program
ASIC program
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COMPANY
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Products A-Z
-Acceleration/emulation
-Allegro AMS Simulator
-Allegro Design Entry CIS
-Allegro Design Entry HDL
-Allegro Design Publisher
-Allegro Design Workbench
-Allegro Package Designer
-Allegro Package SI
-Allegro PCB Design
-Allegro PCB Librarian
-Allegro PCB SI
-Allegro System Architect
-Analog-mixed signal
-Assura DRC
-Assura LVS
-Assura RCX
-Cadence 3D Design Viewer
-Cadence and
Agilent technologies RF IC partnership
-Cadence Chip Optimizer
-Cadence CMP Predictor
-Cadence Litho
Electrical Analyzer
-Cadence Litho Physical Analyzer
-Cadence MaskCompose Suite
-Cadence QRC Extraction
-Cadence SiP Digital Architect
-Cadence SiP Digital Layout
-Cadence SiP Digital SI
-Cadence SiP RF Architect
-Cadence SiP RF Layout
-Cadence Space-Based Router
-CeltIC NDC
-Diva Physical Verification
-Dracula
-Encounter Conformal
Constraint Designer
-Encounter Conformal ECO Designer
-Encounter Conformal
Equivalence Checker
-Encounter Conformal Low Power
-Encounter Library Characterizer
-Encounter RTL Compiler
-Encounter Test
-Encounter Timing System
-Fire & Ice QX
-First Encounter
-Formal analysis
-Incisive Acceleration
and Emulation
-Incisive Design Team family
-Incisive Enterprise family
-Incisive HDL family
-Incisive Unified Simulator
-Incisive XLD
-Incisive XLD Base
-NanoRoute
-NC-SC
-NC-Verilog
-NC-VHDL
-OrCAD Capture
-OrCAD PCB Designer
-OrCAD Signal Explorer
-Other Virtuoso Products
-Palladium series
-Physical Verification System
-Plan-to-Closure Methodology
-PSpice simulation
-Simulation
-SoC Encounter
-Testbench automation
-Verification IP
-Verification management
-Virtuoso AMS Designer Simulator
-Virtuoso Analog
ElectronStorm Option
-Virtuoso Analog
VoltageStorm Option
-Virtuoso Chip Editor
-Virtuoso Digital Implementation
-Virtuoso Layout Migrate
-Virtuoso Multi-Mode Simulation
-Virtuoso Passive
Component Designer
-Virtuoso platform GXL
-Virtuoso platform L
-Virtuoso platform XL
-Virtuoso RET Suite
-Virtuoso RF Designer
-Virtuoso Spectre
Circuit Simulator
-Virtuoso Spectre
RF Simulation Option
-Virtuoso UltraSim
Full-chip Simulator
-VoltageStorm
-Xtreme series
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