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| Supported Interfaces |
| Protocols |
Memories |
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Today's Cadence offering continues a 10 year legacy of advanced, production-proven VIP that has been employed to verify dozens of protocols across thousands of designs. The Cadence memory models (formerly marketed as Denali MMAV memory models) have long been considered to be the "gold standard" in memory interface verification.
The Cadence solution meets the unique needs of IP, SoC, and System-level verification engineers and designers:
- IP developers benefit from support for the latest emerging protocols, the hundreds of automatic protocol checks performed by each VIP, and the confidence in knowing the VIP has been proven in production across multiple designs.
- SoC developers benefit from the broad support for all the complex standard protocols and memory interfaces found on today's SOCs, a common testbench interface spanning the entire VIP and memory offering, and innovative licensing that reduces the cost barrier to multi-protocol verification.
- System developers benefit from Accelerated VIP for unlocking the power of Palladium XP Verification Computing Platform to verify hardware/software integration, and a path toward implementing software-driven verification, a programmer's view of system verification to tests drivers and SoC interfaces concurrently.
Features
- Supports 3rd party simulators
- 30+ supported protocols
- First to market with support for emerging standards such as the AMBA4 family, PCI Express Gen3, SuperSpeed USB, Ethernet 40G/100G, and the MIPI protocols
- Over 15,000 memory device configurations including support for new memory types such as DDR4 SDRAM, Flash ONFI 3.0, Flash PPM, Flash Toggle2NAND, GDDR5, LRDIMM, and Wide I/O SDRAM
- Protocol compliance checking via the CMS and PureSuite solutions
- Assertion suites for formal verification of AMBA and OCP fabrics via Incisive Formal Verifier
- Accelerated VIP for the most widely used complex protocols to support hardware acceleration of large SoCs and hardware/software integration.
- Support for all common testbench languages including SystemVerilog and e
- Support for the Universal Verification Methodology (UVM)
Additional
Protocol Compliance Checking » Accelerated VIP »
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