|
|
|
| Supported Interfaces |
| Protocols |
Memories |
|
|
| | Cadence continues to build on a 10-year legacy of advanced, production-proven VIP that has been used by more than 500 customers to verify dozens of protocols across thousands of designs. Cadence memory models are considered the "gold standard" in memory interface verification. Our VIP Catalog is the smart choice for your next project:
- SoC and system-level verification support
- Mature solution with a full-featured, stable, and consistent user interface and configuration assistance
- Support for 40+ protocols (including the latest emerging protocols) and 6,000 memory models covering 85 manufacturers
- Real-world multi-simulator, multi-language, and multi-methodology support
- Technically advanced and productive solution
Cadence VIP solutions meet the unique needs of IP, SoC, and system-level verification engineers and designers:
- IP developers benefit from mature full-featured VIP, early support for the latest emerging standards, advanced protocol compliance verification with TripleCheck, and assertion-based VIP for formal analysis of bus fabrics
- SoC developers benefit from unrivaled support of protocol and memory interfaces, advanced interconnect monitors for SoC fabrics, and innovative Accelerated VIP (AVIP) that enables an easy transition to hardware acceleration and delivers more than 100x the performance of logic simulation
- System developers benefit from AVIP tuned for embedded use in the Palladium XP Verification Computing Platform to deliver 10,000x faster performance than logic simulation and to accelerate hardware/software integration
Features
- Proven at more than 500 customers across thousands of projects
- 40+ supported protocols
- 6,000 memory models covering 85 manufacturers
- First to market with support for emerging standards for mobile platforms and cloud infrastructure
- Accelerated VIP to support hardware acceleration of large SoCs and hardware/software integration
- Assertion suites for formal verification of SoC fabrics
- Unique Cache Coherent Interconnect Monitor
- Third-generation protocol compliance verification built upon the proven PureSuite and CMS heritage
- Quick and foolproof configuration with the PureView configurator
- Rapid debugging assistance with the unique Trace Debug utility
- Support for all common testbench languages including SystemVerilog, e, SystemC, Verilog, and VHDL
- Support for a range of verification methodologies including UVM, OVM, VMM, eRM, and directed test
- Support for the Cadence Incisive Enterprise Simulator, Synopsys VCS simulator, and Mentor Graphics Questa simulator
Additional Information
Self-Guided TourTest-drive the Cadence VIP Catalog online via hands-on demos at Xuropa.com. |
|
|
|
|