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SuperSpeed USB

Part of the Cadence VIP Catalog

The Cadence SuperSpeed USB Verification IP (VIP) provides a mature, highly capable compliance verification solution for the USB 3.0 Protocol. Used on multiple production designs, the SuperSpeed USB VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The SuperSpeed USB VIP supports PureSuite which provides an easy-to-use, extensive test suite for protocol compliance verification.

Download Cadence Verification IP for USB Protocols Datasheet »

Archived Webinar: USB 3.0 - Verification Challenges and Solutions »

User Type	Cadence VIP Advantages and Differentiation
IP developers	Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs.
SoC developers	One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification.

Capabilities

Full timing, bus functional modeling of USB specification
Models host, device and hub
Full Support to all layers (framework, protocol, link, and physical)
Power Management
Support dual-simplex, four-wire differential signaling and 8b/10b parallel interface
Operates in SuperSpeed, Full, or HighSpeed mode
Supports SuperSpeed Inter-Chip (SSIC) specification
Detailed coverage of functional layers
Complete USB enumeration

Supported Configurations

The USB 2.0 VIP completely models all USB components in the topology, including the host, device and hub.

Layer	Model Highlights
Protocol Layer	Completely models protocol, manages transaction requests and responses. Checks for all the transaction and packet rules.
Interface Layer	Completely models the physical link from the protocol layer to the simulation environment. Supports DP/ DM, UTMI, UTMI+, ULPI and HSIC interfaces. Supports reset, suspend/resume, remote wakeup.
Registers	Stores configuration information and model state. Supports register queries and updates through a testbench interface.

Protocol Compliance

The PureSuite compliance tests for SuperSpeed USB VIP enable designers to dramatically reduce the time and risk associated with functional verification, a task which regularly consumes over 70 percent of the entire chip development cycle. The sheer complexity of new interfaces makes the immediate availability of a robust specification test suite a required element of any design verification effort.