Home > Products > Functional Verification > Cadence VIP Catalog > Serial RapidIO

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Serial RapidIO

Part of the Cadence VIP Catalog

The Cadence Serial Rapid IO (SRIO) Verification IP (VIP) provides a mature, highly capable compliance verification solution for the SRIO Protocol. Used on multiple production designs, the SRIO VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The SRIO VIP supports the unique Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results correlated with the protocol specification.

User Type	Cadence VIP Advantages and Differentiation
IP developers	Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs.
SoC developers	One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification.

Capabilities

Supports SRIO specification versions 1.3, 2.0 and 2.1
Supports x1, x2, x4, x8, x16 lanes configurations
Supports legacy RapidIO commands.
Supports test generation at all protocol layers including logical, transport and physical
Support of IDLE2 sequence
Supports Continuous (CT) and Reliable (RT) traffic support
Provides direct access to configuration registers
Complies with the Unified Verification Methodology (UVM)

Supported Configurations

The SRIO VIP includes models for all protocol layers, with a dedicated agent per layer.

Protocol Layer	Model Highlights
Logical Layer	Completely models protocol Manages transaction requests and completions Checks for all the packet rules
Transport Layer	Completely models protocol Provides bus monitor.
Physical Layer	Completely models protocol Supports flow control. Supports Link and Port initialization
Configuration Registers	Maintains configuration info in a separate memory space Supports register queries and updates through a testbench interface.

Protocol Compliance

The SRIO VIP provides a highly capable protocol compliance verification solution called the Compliance Management System (CMS). CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIP's sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised.