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SATA

Part of the Cadence VIP Catalog

The Cadence SATA Verification IP (VIP) provides a mature, highly capable compliance verification solution for the SATA Protocol. Used on multiple production designs, the SATA VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators.

User Type	Cadence VIP Advantages and Differentiation
IP developers	Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs.
SoC developers	One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification.

Capabilities

Full support of SATA 6Gb/s including speed change negotiation between 1.5Gb/s, 3.0Gb/s, and 6.0Gb/s
Full support of SATA 1.0a and SATA 2.0 Extensions
Supports all protocol layers: Enclosure, Command, Transport, Link, PHY
Selectable pin interface: Serial, 10-bit, PHY
Controllable protocol checkers and passive monitors
Pre-defined traffic libraries
Powerful error injection capability
Cumulative functional coverage reports

Supported Configurations

The SATA VIP completely models all SATA components in the topology, including the host and one or more SATA devices. A generic model conforming to the specification can also be emulated.

Layer	Model Highlights
PHY Layer	Performs the serialization/deserialization of data; also interprets out-of-band signaling used for power up and hot plug detection. Drives the pins at a serial or 10bit interface.
Link Layer	Performs the packet framing, 8b/10b encoding/ decoding, generation and checking of CRC; also handles and checks flow control and data buffering; direct testbench interface into link layer to control and initiate link layer packet traffic.
Transport Layer	Interfaces to the ATA register file, interpreting commands and giving link layer blocked tasks; direct testbench interface into transport layer to control and initiate transport layer pack traffic.
Command Layer	Defines sequences of Transport layer actions that are performed to execute ATA commands.
Enclosure Layer	Defines a means to support industry-standard SAF_TE (SCSI Accessed Fault-Tolerant Enclosures) and SES (SCSI Enclosure Services) enclosure services. It improves the functionality of SATA storage subsystems.

Protocol Compliance

The SATA VIP includes a monitor programmed with hundreds of automatic protocol checks to verify that the design-under-test complies with the protocol specification.