Part of the Cadence VIP Catalog
The Cadence SAS Verification IP (VIP) provides a mature, highly capable compliance verification solution for the SAS Protocol. Used on multiple production designs, the SAS VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The SAS VIP supports the unique
Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results correlated with the protocol specification.
| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification. |
Capabilities
- Programmable as SAS Initiator model
- Programmable as SAS Target model
- SSP and SMP protocol checking
- Supports and checks for proper timing and misalignment errors in PHY
- Supports primitive sequence generation and transmission at all layers
- Configurable pattern generation for random, directed or erroneous patterns
- Configurable setup for scoreboard integration
- Checkers verify protocol timing checks and functional accuracy at each layer
- Supports layered transmitter and receiver states
- Includes encoder/decoder, scrambler, and CRC checking
- Scalable to test multi-port SAS hosts
- Includes protocol coverage report to identify protocol verification
- Compliance Management System automates protocol compliance verification
- Generates constrained-random bus traffic
- Responds to bus traffic as a slave
- Transmits snoop transactions by mimicking a dummy interconnect
- Monitors, checks, and collects coverage on bus traffic and interconnect
Supported Configurations
The SAS VIP may be used to verify Initiator and Device designs. The VIP may be used to generate and drive traffic as an initiator or respond as a device. A monitor watches the traffic to check for protocol violations. SAS Wide Ports are supported as well as multi-initiator topologies.
Protocol Compliance
The SAS VIP provides a highly capable protocol compliance verification solution called the
Compliance Management System (CMS). CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIP's sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Take a Self-Guided Tour
Test drive this VIP on-PCIe via the
hands-on demos at Xuropa.com