Part of the Cadence VIP Catalog
The Cadence PLB Verification IP (VIP) provides a mature, highly capable compliance verification solution for the PLB Protocol. Used on multiple production designs, the PLB VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The PLB VIP supports PureSuite which provides interactive, graphical analysis of coverage results correlated with the protocol specification.
| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification. |
Capabilities
- Full timing, bus functional models for PLB-4 or PLB-6 devices
- Separate and configurable address bus, read data bus, and write data bus for each bus master
- Split/deferred completion scenarios and out-of-order data returns
- Separate read/write bus transfer qualifiers for overlapping read/write data
- Byte, half word, and word transfers (as well as unaligned half-word transfers and 3-byte transfers using byte enables)
- All masters and slaves attach to the PLB as 128-bit, 64-bit, and 32-bit devices. Slaves may
support 8-bit and 16-bit bus widths if required
- All high-speed PLB features
- Assertion library linked to configurable models supporting all valid topologies
- Controllable protocol checkers, monitors for interoperability testing
- Pre-defined traffic libraries with user-customizable packet generation
- Powerful error injection/detection capability
- Cumulative functional coverage reports
- Transaction logging
Supported Configurations
The PLB VIP provides a sophisticated data generation engine to help drive defined, pseudo-random bus traffic at all layers. Injected errors and error conditions are flagged and recovered according to PLB
specifications. The highly integrated nature of VIP’s model behavior and data generation engine applies a sophisticated context-sensitive data generation approach to test plan execution. This enables direct translation from test plan definition to implementation, greatly accelerating the verification task and your overall verification productivity. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the DUT. In addition to interacting at the pin level, the PLB VIP has a procedural interface to directly load or save a memory image, read or write memory words, or trigger callbacks at different stages of data flow.
- Configurable test plans reduce verification efforts
- Pre-built coverage and sequence libraries
- Integration with third-party verification planners
Additional features:
- Complete assertion library with thousands of runtime checks
- Configurable BFM and protocol monitor
- Constrained random traffic generation
- Pre-defined sequence libraries
- Pre-built libraries enabling coverage-driven verification
- Monitors for interoperability testing
- Powerful error injection capability
- Cumulative functional coverage reports
Protocol Compliance
The PureSuite compliance tests for PLB enable designers to dramatically reduce the time and risk associated with functional verification, a task which regularly consumes over 70 percent of the entire chip development cycle. The sheer complexity of new interfaces makes the immediate availability of a robust specification test suite a required element of any design verification effort.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Take a Self-Guided Tour
Test drive this VIP on-line via the
hands-on demos at Xuropa.com