Part of the Cadence VIP Catalog
The Cadence PCI Express Verification IP (VIP) provides a mature, highly capable compliance verification solution for the PCI Express 1.1, 2.0, and 3.0 Protocols. Used on multiple production designs, the PCI Express VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The PCI Express VIP supports
PureSuite which provides thousands of test cases to simulate PCI Express traffic and check for compliance with the PCI Express specifications.
Download Cadence Verification IP for PCI Express Protocols
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| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification. |
| System developers |
Use accelerated VIP to take advantage of the speed of Palladium hardware systems to verify hardware/software integration. In addition, the Virtual Register Interface enables software to drive the testbench. |
Capabilities
- Supports PCI Express specification versions 1.0a, 1.1, 2.0, 2.1 and 3.0
- Supports Single-Root (SR) IOV and Multi-Root (MR) IOV specifications
- Supports Serial and PIPE 1.0, 2.0 and 3.0 interfaces
- Enables verification of PCIe Endpoints, Root Complexes, Switches, and Bridges.
- Provides transaction layer, data Link layer, and PHY layer testing
- Supports all post-2.0 specification ECNs
- Provides complete PCIe hierarchy enumeration
- Provides direct access to configuration registers
- Supports compliance test suite including thousands of test sequences
- Complies with the Unified Verification Methodology (UVM)
Supported Configurations
The PCIe VIP includes models for all PCIe devices in the topology, including the root complex, switch, endpoint and PCIe-to-PCI bridge. A generic device conforming to the specification can also be emulated. Composite configurations by port, function or virtual channel are supported.
| Transaction Layer |
Completely models protocol
Manages transaction requests and completions
Checks for all the packet rules
Supports message requests as well as multi-functions. |
| Link Layer |
Completely models protocol
Manages data integrity (CRC)
Supports flow control initialization. |
| Physical Layer |
Completely models protocol
Supports power-on-state machines and training sequence, and clock recovery
8b/10b encoding and data scrambling |
| Configuration Registers |
Maintains configuration info in a separate memory space
Supports register queries and updates through a testbench interface. |
Protocol Compliance
The
PureSuite compliance tests for PCI Express enable designers to dramatically reduce the time and risk associated with functional verification, a task which regularly consumes over 70 percent of the entire chip development cycle. The sheer complexity of new interfaces makes the immediate availability of a robust specification test suite a required element of any design verification effort.
Verification Platform Choice
Cadence VIP provides users the greatest range of platforms to use for PCI Express verification. In addition to the simulation VIP described above, Cadence also provides accelerated VIP for the Palladium XP Verification Computing Platform. Details on each are provided below.
Hardware Acceleration
Cadence supports accelerated verification using the
Palladium XP Verification Computing Platform. This provides users with the performance needed for system level verification. It also enables users to trade off performance for verification capability as they progress from block to chip to system level verification.
Cadence Accelerated VIP supports two different use modes: DirectC and UVM acceleration. The DirectC acceleration mode provides the absolute highest performance without a testbench. The UVM acceleration mode provides simulation environment reuse and a higher degree of verification capability relative to DirectC. This enables users to trade off performance and verification capability to meet their needs at each stage in the design process.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Customer Feedback
"We brought up the CMS compliance test suite in our verification environment in just a day. Our team was impressed with the rapid results. We identified a number of failures right away and we’re now working to dramatically expand our regression runs to take full advantage of the CMS."
Mike Bartley
Test and Verification Manager, ClearSpeed
"We are using Denali's PureSpec verification IP extensively in the development of our PCI Express designs, and we are very pleased with the quality and completeness of this product, Ensuring compliance with the PCI Express specification is also a critical task, and we are now seeing value in Denali's PureSuite product for PCI Express compliance verification."
Shrenik Mehta
Director of Frontend Technologies for ASIC's Processors and OpenSPARC® Program at Sun Microsystems
Take a Self-Guided Tour
Test drive this VIP on-PCIe via the
hands-on demos at Xuropa.com