Part of the Cadence VIP Catalog
The Cadence PCI Express Verification IP (VIP) provides a mature, highly capable compliance verification solution for the PCI Express 1.1, 2.0, and 3.0 Protocols. Used on multiple production designs, the PCI Express VIP is a proven solution enabling efficient and thorough verification. The VIP supports simulation and hardware acceleration platforms making it applicable to IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators.
Download Cadence Verification IP for PCI Express Protocols
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| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
Broad selection of interface VIP and memory models covers the spectrum of SoC protocols and provides a common testbench interface to boost productivity. New accelerated VIP (AVIP) enables performance that is often hundreds to thousands of times greater than with simulation, as is needed for SoC/System level verification. |
| System Developers |
Use accelerated VIP to take full advantage of the speed of Palladium hardware verification systems for performance levels great enough to perform hardware/software integration. |
Capabilities
- Supports PCI Express specification versions 1.0a, 1.1, 2.0, 2.1 and 3.0
- Supports Single-Root (SR) IOV and Multi-Root (MR) IOV specifications
- Supports NVM Express specification (Optimized PCI Express SSD Interface)
- Supports Serial and PIPE 1.0, 2.0 and 3.0 interfaces
- Enables verification of PCIe Endpoints, Root Complexes, Switches, and Bridges.
- Provides transaction layer, data Link layer, and PHY layer testing
- Supports all post-2.0 specification ECNs
- Provides complete PCIe hierarchy enumeration
- Provides direct access to configuration registers
- Supports compliance test suite including thousands of test sequences
- Complies with the Unified Verification Methodology (UVM)
Supported Configurations
The PCIe VIP includes models for all PCIe devices in the topology, including the root complex, switch, endpoint and PCIe-to-PCI bridge. A generic device conforming to the specification can also be emulated. Composite configurations by port, function or virtual channel are supported.
| Transaction Layer |
Completely models protocol
Manages transaction requests and completions
Checks for all the packet rules
Supports message requests as well as multi-functions. |
| Link Layer |
Completely models protocol
Manages data integrity (CRC)
Supports flow control initialization. |
| Physical Layer |
Completely models protocol
Supports power-on-state machines and training sequence, and clock recovery
8b/10b encoding and data scrambling |
| Configuration Registers |
Maintains configuration info in a separate memory space
Supports register queries and updates through a testbench interface. |
Protocol Compliance
TripleCheck IP Validator helps verify advanced new protocols like the PCI Express 3.0 specification. TripleCheck works in conjunction with Cadence VIP to make interface verification quick and efficient by providing the three things that verification engineers need most: a test suite, coverage model, and verification plan. TripleCheck integrates with the Cadence VIP Catalog's PureView GUI to help users get started quickly. When the user configures a VIP with PureView, the TripleCheck test suite, coverage model, and verification plan are automatically configured to match the VIP.
Accelerated VIP
To enable users to verify such large designs, Cadence provides the
Palladium Verification Computing Platform in conjunction with high-performance
accelerated verification IP (AVIP). By facilitating the high speed transfer of interface traffic through a design under test in Palladium, Cadence AVIP enables engineering teams to dramatically boost the verification performance of designs at any integration level: IP, subsystem, SoC, and system-level. And, by employing an off-the-shelf solution from Cadence, verification teams can focus on finding bugs instead of developing undifferentiated infrastructure.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Customer Feedback
"We brought up the CMS compliance test suite in our verification environment in just a day. Our team was impressed with the rapid results. We identified a number of failures right away and we’re now working to dramatically expand our regression runs to take full advantage of the CMS."
Mike Bartley
Test and Verification Manager, ClearSpeed
Take a Self-Guided Tour
Test drive this VIP on-PCIe via the
hands-on demos at Xuropa.com