Part of the Cadence VIP Catalog
The Cadence OCP Verification IP (VIP) provides a mature, highly capable compliance verification solution for the OCP Protocol. Used on multiple production designs, the OCP VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence Incisive Enterprise Simulator
and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The OCP VIP supports the unique Compliance Management System
(CMS) which provides interactive, graphical analysis of coverage results correlated with the protocol specification.
||Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
||One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification.|
||Use accelerated VIP to take advantage of the speed of Palladium hardware systems to verify hardware/software integration. In addition, the Virtual Register Interface enables software to drive the testbench.
- Verifies OCP-based devices and IP
- Protocol checker fully compliant with the OCP 2.2 specification
- Cadence is committed to supporting OCP 3.0 once specifications are available
- Configurable as master/slave (or monitor only)
- Master can drive the full set of commands
- Slave can be configured as RAM
- Full multi-threading and tagging support
- Full 2D burst model, non-blocking flow control support, asynchronous reset, and clock-enable mechanism
- Automatic OCP traffic generation including error injection
- Built-in functional coverage measurement and reporting with automatic correlation to specification sections
- Large set of supplied OCP tests, each with user-controllable randomization ranging from deterministic to fully random
- Built-in reference burst compliance test library
- Self-test option to run test cases using only the VIP for OCP (prior to design-under-test availability)
The OCP VIP provides a highly capable protocol compliance verification solution called the Compliance Management System
(CMS). CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIP's sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised.
Verification Platform Choice
Cadence VIP provides users the greatest range of platforms to use for OCP verification. In addition to the simulation VIP described above, Cadence also provides assertion based verification IP (ABVIP) and accelerated VIP for the Palladium Verification Computing Platform. Details on each are provided below.
Cadence's OCP Assertion Based Verification IP (ABVIP) is available for OCP2.2. ABVIP takes advantage of the speed and efficiency of Incisive Formal Verifier
(IFV) to provide an easy to use, highly predictable path to verification closure. Through powerful formal analysis techniques the OCP ABVIP enables design engineers to easily verify OCP functionality and compliance since there is no need for them to create test stimulus.
ABVIP contains complete and optimized constraint and assertion models and a set of pre-verified PSL properties and cover checks. They are used for interface monitoring in simulation and exhaustive formal analysis of protocol compliance with IFV.
Cadence supports accelerated verification using the Palladium XP Verification Computing Platform
. This provides users with the performance needed for system level verification. It also enables users to trade off performance for verification capability as they progress from block to chip to system level verification.
Cadence Accelerated VIP supports two different use modes: DirectC and UVM acceleration. The DirectC acceleration mode provides the absolute highest performance without a testbench. The UVM acceleration mode provides simulation environment reuse and a higher degree of verification capability relative to DirectC. This enables users to trade off performance and verification capability to meet their needs at each stage in the design process.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
The following methodologies may be used in conjunction with the VIP:
Take a Self-Guided Tour
Test drive this VIP on-line via the hands-on demos