Part of the Cadence VIP Catalog
The Cadence VIP Catalog Memory Models (formerly known as Denali MMAV) are the industry's standard solution for verifying memory interfaces and ensuring system correctness. The models dramatically enhance verification by enabling users to observe and operate on system-level data transactions during simulation. This approach optimizes regressions and accelerates overall verification process.
New models are continually being added to the catalog with recent additions including Wide I/O SDRAM, DDR4SDRAM, LRDIMM, GDDR5, Flash ONFI 3.0, Flash PPM, and Flash Toggle2NAND. The models support a wide range of advanced verification features to aid debugging - from assertions and callbacks to catch erroneous data transactions, to logical address mapping, error injection and transaction logging.
Try a hands-on demo of this product at Xuropa.com»
Capabilities
- Vendor Certified high quality memory models
- Advanced verification features
- Second-sourcing options with variable memories
- Support for all commercial verification tools, languages, & methodologies
Supported Memory Types
The memory models include support for various technologies and certified from various vendors including:
- All DRAM including DDR1, DDR2, DDR3, Mobile SDR/DDR, Mobile DDR2, GDDR2, GDDR3, GDDR4, GDDR5, etc.
- All SRAM including QDR, PSRAM, etc.
- All Flash including NOR, NAND, OneNAND, ONFi 2.2, Perfect NAND, Toggle NAND, LBA NAND, etc.
- All Media Card memories including CE-ATA, CompactFlash, SDCard, SD3.0, eSD(embedded SDCard), Memory Stick, Memory Stick Pro, MMC, eMMC 4.4, etc.
Simulation
The Cadence memory models provide the most complete solution for modeling and simulating memory. Cadence continues to provide the highest quality models for any memory device, in any verification environment in support of over 500 leading edge companies.
The models utilize a powerful and effective approach to modeling memory. The generic functionality of various memory classes and architectures are captured in a set of highly optimized 'C' models. The vendor-specific features and timing for any particular memory device are defined within a SOMA (Specification of Modeling Architecture) file. Once the memory model objects are linked into the simulation environment, modeling any type of memory is as simple as referencing the appropriate SOMA file for that particular memory device. The models automatically monitor all the timing and protocol requirements specified by the memory vendor.
The memory model objects are integrated to all popular simulation/verification environments, and Cadence maintains a comprehensive database of over 15,000 SOMA files online at eMemory.com.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Resource
2010 Enhancements
Sanjiv Kumar presents an in-depth look at the memory model architecture and why it is the industry's standard solution for verifying memory interfaces and ensuring system correctness. Sanjiv covers how to enhance overall verification process as well as many of the model features, including: peek/poke, load/restore, error injection, memory and transaction callback, assertions report generation, errors configurability and more...
View Webcast Now!»
Utilizing Callback Features in MMAV
The webcast presents several examples of using callbacks in a SystemVerilog testbench in a variety of advanced verification methodologies.
View Webcast Now!»
Customers
"Today's SoC design specifications necessitate high-quality IP and VIP and Denali's solutions and expertise unlike any other vendor. We were pleased with the unmatched performance and overall ease of integration of Denali's
Databahn memory controllers into our chip design. We used Databahn controller and MMAV in our design to support our required DDR2 memory interface and
TSMC's 65nm CMOS technology. During the design and verification phases, we found that Denali's IP and VIP were easy-to-use and to integrate which facilitated our very fast design cycle."
Rafy Carmon
Vice President
Precello Ltd.
"Wintegra customers are faced with challenging design specifications for today's programmable multi-protocol networking solutions and in the Service Provider access equipment market. Utilizing Denali's MMAV we were able to accelerate our time-to-market by verifying our DDR memory system quickly and deliver high-quality WinPath2 processors."
Yoram Yeivin
Vice President of Engineering
Wintegra, Inc.
"AppliedMicro values working with leading IP providers, such as Denali, who can provide high-quality products to help us achieve our design requirements in the most cost-effective manner. In order to get to market quickly with lower risk of integration errors, AppliedMicro chose Denali verification IP architected for seamless integration into our advanced SystemVerilog design and verification methodology. Denali's products' performance and integration gives us confidence that our end-products will properly interoperate with these industry standard interfaces."
Amal Bommireddy
Vice President of Engineering
AppliedMicro