The industry’s most comprehensive portfolio of vendor-certified memory models
The memory subsystem is a core component of any SoC and can affect the performance and cost of your end product. Cadence Memory Model Verification IP (VIP) provides a comprehensive solution for verifying memory interfaces and ensuring system correctness.
Download the Cadence Verification IP for Memories Datasheet »
Our high-quality, vendor-certified memory models support all major verification languages, methodologies, and simulators. Using Cadence memory models, engineering teams can accelerate IP, SoC, and system-level verification while being assured of product quality.
Cadence Memory Model VIP allows you to observe and operate on system-level data transactions during simulation. This approach is key to optimizing regressions and reducing the overall verification effort.
Features and Benefits
Modeling and simulation
- Automatically monitors all timing and protocol requirements specified by the memory vendor
- Leverages a comprehensive online database of more than 5,000 specification of modeling architecture (SOMA) files
Advanced verification
- Supports robust assertions, error configurability, transition callbacks, assertion reports, and creation of system memory
- Built-in address manager simplifies assembly of discrete memory components
- Second-sourcing option allows you to verify designs with various memories from more than one vendor
PureView debugging
- Allows you to view and edit memory contents during post-simulation analysis
- Accelerates waveform-level debugging
