Part of the Cadence VIP Catalog
The Cadence MIPI M-PHY Verification IP (VIP) provides a mature, highly capable compliance verification solution for the MIPI M-PHY Protocol. Used on multiple production designs, the MIPI M-PHY VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators.
| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification. |
Capabilities
- Complies with MIPI M-PHY specification revision v0.80
- Supports M-PHY Type1 and Type2
- Supports Signaling Interface (MPI)
- Supports all HS-GEARs and RATE series
- Supports ACTIVATED SAVE states (SLEEP & STALL) and Hibernate ("HIBERN8") state
- Supports Distribution and Merging data over 1 to 4 lanes
- Generate constrained-random stimuli for Data and Control frames
- Monitor, check, and collect coverage results
- User-controlled error injection
- Complies with the Unified Verification Methodology (UVM)
Supported Configurations
The MIPI M-PHY VIP includes a standalone models for the PHY that can be integrated to the different MIPI applications protocols like DigRF, UniPro and CSI3.
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| M-PHY Layer | Completely models
Automatic Link Training
Low speed and High speed operation
Supports Monitor unit
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Protocol Compliance
The MIPI M-PHY VIP includes a monitor programmed with numerous automatic protocol checks to verify that the design-under-test complies with the protocol specification.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Customer Feedback
"The MIPI Alliance of over 200 member companies develops interface specifications which drive consistency in processor and peripheral interfaces, promoting reuse and compatibility in mobile devices. As a longtime contributing member, Cadence has helped advance the evolution of the several MIPI protocols and their rapid adoption by IP and SoC companies."
Joel Huloux
MIPI Alliance, Inc
Take a Self-Guided Tour
Test drive this VIP on-line via the
hands-on demos at Xuropa.com