Part of the Cadence VIP Catalog
The Cadence I2C Verification IP (VIP) provides a mature, highly capable compliance verification solution for the I2C Protocol. Used on multiple production designs, the I2C VIP is applicable for IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The I2C VIP supports the unique
Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results correlated with the protocol specification.
| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
One consistent testbench interface spans the entire Cadence VIP Catalog ensuring straightforward chip level verification. Innovative licensing makes it affordable to perform multi-protocol verification. Also compatible with the extensive Cadence Memory Portfolio for full SoC verification. |
Capabilities
- Supports I2C Bus Specification Revision 2.1
- Generate and drive bus traffic as an I2C MASTER
- Respond to bus traffic as an I2C SLAVE
- Monitor, check, and cover I2C bus traffic
- Monitors, checks, and collects coverage on bus traffic
Supported Configurations
The I2C VIP may be used to verify Master and Slave designs. The designs may be any combination of multiple master, slave, and master/slave.
Protocol Compliance
The I2C VIP provides a highly capable protocol compliance verification solution called the
Compliance Management System (CMS). CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIP’s sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Take a Self-Guided Tour
Test drive this VIP on-line via the
hands-on demos at Xuropa.com