Part of the Cadence VIP Catalog
The Cadence Ethernet Verification IP (VIP) provides a mature, highly capable compliance verification solution for the Ethernet Protocol. Used on multiple production designs, the Ethernet VIP is a proven solution enabling efficient and thorough verification. The VIP supports simulation and hardware acceleration platforms making it applicable to IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence
Incisive Enterprise Simulator and also the Synopsys VCS® and Mentor Graphics Questa® simulators. The ETHERNET VIP supports the unique
Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results correlated with the protocol specification.
| IP developers |
Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
| SoC developers |
Broad selection of interface VIP and memory models covers the spectrum of SoC protocols and provides a common testbench interface to boost productivity. New accelerated VIP (AVIP) enables performance that is often hundreds to thousands of times greater than with simulation, as is needed for SoC/System level verification. |
| System Developers |
Use accelerated VIP to take full advantage of the speed of Palladium hardware verification systems for performance levels great enough to perform hardware/software integration. |
Capabilities
- Verifies Ethernet PHY and MAC devices
- Compliance Management System (CMS) automatically attains high functional coverage
- Operates in PHY and MAC orientations
- Verifies both single- and multi-port Ethernet devices
- Supports the widest range of Ethernet interfaces
- Supports 10Mb, 100Mb, 1Gb, and 10Gb bandwidths
- Enables and supports metric-driven verification (MDV)
- Fully customizable to meet each DUT's specific needs including independent configuration of each port
- Powerful constrained-random generation supports multiple Ethernet packet types including error injection
- Supports full duplex and half duplex operating modes
- Supports the management interface (MIB)
- Supports auto-negotiation features
- Built-in configurable scoreboard to measure data integrity
Supported Configurations
The Ethernet VIP includes models for both PHY and MAC devices and supports a wide range of interfaces including 10Mb, 100Mb, 1Gb and 10Gb/40Gb bandwidths. It also provides support for both PHY and MAC orientations and verifies both single and multi-port Ethernet devices.
| Verification Support |
|---|
| MII | • | | |
| RMII | • | | |
| SMII | • | | |
| GMII | | • | |
| RGMII | | • | |
| SGMII | | • | |
| TBI | | • | |
| 1GBASE-KX | | • | |
| RTBI | | | • |
| XAUI | | | • |
| XGMII | | | • |
| XSBI | | | • |
| 10GBASE-KX4 | | | • |
| 10GBASE-KR | | | • |
Protocol Compliance
The ETHERNET VIP provides a highly capable protocol compliance verification solution called the
Compliance Management System (CMS). CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIP's sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised.
Accelerated VIP
To enable users to verify such large designs, Cadence provides the
Palladium Verification Computing Platform in conjunction with high-performance
accelerated verification IP (AVIP). By facilitating the high speed transfer of interface traffic through a design under test in Palladium, Cadence AVIP enables engineering teams to dramatically boost the verification performance of designs at any integration level: IP, subsystem, SoC, and system-level. And, by employing an off-the-shelf solution from Cadence, verification teams can focus on finding bugs instead of developing undifferentiated infrastructure.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
- SystemVerilog
- e
- SystemC
- Verilog
- VHDL
- C,C++
The following methodologies may be used in conjunction with the VIP:
Take a Self-Guided Tour
Test drive this VIP on-line via the
hands-on demos at Xuropa.com