Part of the Cadence VIP Catalog
The Cadence Verification IP (VIP) for the ARM® AMBA® protocol family provides a mature, highly capable compliance verification solution for the complete set of AMBA protocols including AMBA 4. This includes support for the AMBA Coherency Extensions (ACE), Stream, AXI3/4, AHB and APB. Having verified well over 2,000 production designs, you can depend on the AMBA VIP's maturity. The VIP supports simulation, formal analysis, and hardware acceleration platforms making it applicable to IP, SoC, and system-level verification. The VIP is compatible with the industry standard Universal Verification Methodology (UVM) and runs on the Cadence Incisive Enterprise Simulator
as well as the Synopsys VCS® and Mentor Graphics Questa® simulators. Cadence also provides the Compliance Management System
(CMS) which provides interactive, graphical analysis of coverage results correlated directly to the protocol specification.
Download AMBA Family Datasheet »
Download Cadence Coherency Verification Technical Brief »
View video of the Exhibitor Forum presentation by ARM and Cadence at DAC 2011 »
||Take advantage of thousands of automatic protocol checks performed by the VIP and the extensive compliance test suite. Be confident in knowing the VIP has been used in thousands of production designs. |
||Broad selection of interface VIP and memory models covers the spectrum of SoC protocols and provides a common testbench interface to boost productivity. New accelerated VIP (AVIP) enables performance that is often hundreds to thousands of times greater than with simulation, as is needed for SoC/System level verification. Interconnect Validator verifies the interconnect fabrics that connect IP blocks and subsystems within an SoC.
||Use accelerated VIP to take full advantage of the speed of Palladium hardware verification systems for performance levels great enough to perform hardware/software integration.
- Supports AMBA 4 and AMBA 3 including ACE, Stream, AXI3/4, AHB and APB
- Interconnect Validator verifies coherent and non-coherent interconnects
- Compliance Management System automates protocol compliance verification
- Generates constrained-random bus traffic
- Responds to bus traffic as a slave
- Transmits snoop transactions by mimicking a dummy interconnect
- Monitors, checks, and collects coverage on bus traffic and interconnect
- Includes hundreds of assertions for formal compliance verification
- Supports SystemVerilog, e and SystemC language test benches
- Operates in both simulated and accelerated platforms for ultimate flexibility
- Complies with the Unified Verification Methodology (UVM)
The VIP provides agents to verify all AMBA components including masters, slaves, arbiters and decoders. The VIP supports all configurations including multiple masters, multiple slaves and combinations of masters and slaves. Supports all AHB configurations including Lite and Multi-Layer.
The AMBA VIP provides a highly capable protocol compliance verification solution called the Compliance Management System
. CMS includes a verification plan and a full suite of tests. It drives defined, constrained random bus traffic at all layers to offload this time consuming task from you. Injected errors and error conditions are flagged and recovered according to AMBA specifications. The VIP's sequence generation engine applies a context-sensitive approach to test plan execution. This greatly speeds the verification task and increases verification productivity. A cumulative coverage database ensures that the design under test is sufficiently exercised.
Cadence Interconnect Validator
verifies the interconnect fabrics that connect IP blocks and subsystems within an SoC. Interconnect Validator works in conjunction with VIP components to model and monitor all ports on an SoC’s interconnect. Sophisticated algorithms track data items as they are transported through the interconnect to their destinations. Arbitration of traffic is accounted for as well as data transformations such as upsizing, downsizing, and splitting.
Verification Platform Choice
Cadence VIP provides the greatest flexibility for AMBA verification. In addition to the simulation VIP previously described, Cadence provides assertion based verification IP for use in formal verification and accelerated VIP for use with the Palladium Verification Computing Platform. More information on each are provided below.
Cadence's AMBA Assertion Based Verification IP (ABVIP) is available for AXI and AHB. ABVIP takes advantage of the speed and efficiency of the Incisive Formal Verifier
platform (IFV) to provide an easy to use, highly predictable path to verification closure. Through powerful formal analysis techniques the AMBA ABVIP enables design engineers to easily verify AXI and AHB functionality and compliance since there is no need for them to create test stimulus.
ABVIP contains complete and optimized constraint and assertion models and a set of pre-verified PSL properties and cover checks. They are used for interface monitoring in simulation and exhaustive formal analysis of protocol compliance with IFV.
To enable users to verify such large designs, Cadence provides the Palladium Verification Computing Platform
in conjunction with high-performance accelerated verification IP
(AVIP). By facilitating the high speed transfer of interface traffic through a design under test in Palladium, Cadence AVIP enables engineering teams to dramatically boost the verification performance of designs at any integration level: IP, subsystem, SoC, and system-level. And, by employing an off-the-shelf solution from Cadence, verification teams can focus on finding bugs instead of developing undifferentiated infrastructure.
Language & Methodology Support
The following languages may be used in conjunction with the VIP:
The following methodologies may be used in conjunction with the VIP:
"We brought up the CMS compliance test suite in our verification environment in just a day. Our team was impressed with the rapid results. We identified a number of failures right away and we're now working to dramatically expand our regression runs to take full advantage of the CMS."
- Mike Bartley, Test and Verification Manager, ClearSpeed
"The strength of AMBA has always been centered around its broad industry adoption and EDA support. As a leading EDA company, Cadence has enabled the embedded community with AMBA-based design and verification tools for years, and we look forward to their continued strong support for our newest AMBA 4 on-chip interconnect specification."
- Keith Clarke, Vice President and General, Fabric IP Processor Division at ARM
Take a Self-Guided Tour
Test drive this VIP on-line via the hands-on demos