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Cadence TLM-Driven Design and Verification Methodology 

Transaction-level modeling (TLM) takes design and verification to the next abstraction level, removing extraneous implementation detail so that engineers can focus on functionality. A TLM-driven methodology leverages high-level synthesis, metric-driven verification, and advanced ECO capabilities to enable: 10x faster IP reuse; 2x faster verification turnaround; 30-50% shorter debug cycle; and much broader micro-architecture exploration to optimize tradeoffs among latency/throughput, power consumption, and size.
High-Level Synthesis
The main barrier to widespread adoption of TLM-based design has been that automated synthesis has not been able to deliver quality of results (QoR) equal to what handwritten RTL can achieve.

Cadence® C-to-Silicon Compiler embeds Encounter® RTL Compiler production synthesis under-the-hood to measure the effects of different tradeoffs utilizing the target technology library. This enables C-to-Silicon Compiler to deliver QoR that consistently meets or beats that of handwritten RTL and that will converge predictably on design goals in implementation.

For designs targeting FPGAs, C-to-Silicon Compiler utilizes an API into the leading FPGA device synthesis tools. In addition, C-to-Silicon Compiler offers a rich graphical environment to analyze the design and make manual tradeoffs, providing fine control even from a high level of design.

Metric-Driven Verification Methodology
The Incisive® metric-driven verification methodology has been extended to include verification of the TLM design description. Because it is built on top of the existing methodology, it fits into existing verification infrastructures.

The metric-driven verification methodology allows the bulk of functional verification to be run at a much higher level than RTL, which means faster runtimes and more productive debugging. As more detail gets added in the form of RTL and signal-level interfaces, the testbench can be reused, adding tests to verify the new detail in implementation. This is all driven by a verification plan that tests every piece of functionality at the highest level of abstraction that is available, where runtimes and debug are much faster.

TLM-GDSII Implementation with ECOs Throughout
Cadence offers the industry’s only full solution for implementing a TLM design in silicon. C-to-Silicon Compiler embeds RTL Compiler logic synthesis to ensure that the RTL generated will achieve the desired QoR. C-to-Silicon Compiler also generates all the necessary collateral to run RTL Compiler and begin Cadence RTL-GDSII implementation.

And if an engineering change order (ECO) is required while the design is progressing through implementation, the fix can be applied and verified on the TLM design and patched forward to any point in the implementation flow, including post-mask. This connected flow delivers the most predictable design closure available from TLM-to-GDSII.