System level design concepts and automation are evolving at a fast pace. The recent emergence of high level synthesis has reinvigorated the use of SystemC for modeling designs and provided new opportunities to speed functional verification. Adopting these advanced technologies can be challenging from a learning perspective, and to optimize the results of the design, as well as schedule and cost of deployment. Methodology is a key to planning a strategy for adoption, and this book provides the first unified methodology considering high level synthesis and functional verification. It contains effective strategies and technical examples that eases absorption of complexities of system level design.
NEW! Japanese translation created with Professor Saito at Aizu University in Japan. TLM-driven Design and Verification Methodology book now in use in Graduate courses at Columbia and Aizu Universities.
NEW! TLM book now in Japanese! Get your copy today »
"The TLM D&V methodology described in this book explains how to ensure 'true' IP reuse by enabling the user to model at a high level of abstraction (using SystemC TLM) and by guaranteeing the required quality of results via methodology automation. The book demonstrates how support of the OSCI SystemC synthesizable subset enables not only adherence to industry standards, but also portability of source code. It describes efficient modeling of both control FSM and algorithmic datapaths in a single, high-level model as well as integration and co-verification with custom legacy RTL blocks where necessary. The book also reveals how TLM abstractions facilitate easy integration with virtual platforms for early software development. This book is a very good primer for TLM technology and should be read by anybody wanting to adopt it."
Soujanna Sarkar, Design Manager, Wireless Business Unit, Texas Instruments Inc.
"Several conferences and print articles have recently identified education as one of the biggest problems related to getting the latest EDA technologies and methodologies into the hands of the people that can use and benefit from them. This is why Cadence decided to publish their ongoing work in the creation of a methodology that enables efficient and effective migration from an abstract transaction-level model into an RTL model. This methodology includes both the design flow and the verification flow. I was delighted to have been asked to help put this important work together. This book should enable many people to realize the flow being described."
Brian Bailey, Brian Bailey - EDA Consultant and Freelance Writer
"Cadence has done an outstanding job in describing the application of TLM-driven design and verification to reduce the growing gap between design complexity and design productivity. This book provides a complete, practical guide to this new design paradigm and is a must read for any design team considering the move from RTL to ESL."
Tom Sandoval, CEO, Calypto Design Systems
"SystemC has the potential to change how the chips are designed and how the embedded software is developed. The TLM based design and verification methodology from Cadence, along with the tools to support it indicates the commitment of Cadence to raise the abstraction of chip design and provide the long awaited productivity gains to tackle the ever growing complexity in chip design process. CircuitSutra, as a SoC modeling services partner to Cadence, is all set to play an important role in the future of Semiconductor industry."
Umesh Sisodia, CEO, CircuitSutra, Inc.
"The adoption of high level C/C++ based models of hardware coupled with Imperas' OVP simulation technology allows systems to be simulated sooner and faster while paving the way for the next generation of hardware/software verification solutions based on virtual platforms. This Cadence book should be essential reading for developers adopting the Cadence ESL methodology."
Simon Davidmann, President and CEO, Imperas Software Ltd.
"This book is an excellent resource for understanding a flow encompassing both the design and verification using an ESL approach. Although, the methodology is somewhat Cadence specific, I believe there are a lot of good generalities to be taken away that work with other EDA tools as well. The book does a superb job of covering both the implementation (high level synthesis) and verification (UVM driven) aspects using a multi-language approach. I really enjoyed how the authors explain some of the organizational changes that need to occur, and how RTL engineers are an integral part of this process. The proposed methodology appears to be at the exact right time for industry adoption. I highly recommend any SoC teams take time to read this book."
David C Black, Practice Leader for XtremeEDA Corporation's ESL Consulting
"The next frontier for IP reuse involves raising the level of abstraction for design capture above today's mature RTL methodologies. The benefit of transaction-level design are two-fold: permitting architectural reuse while reducing the complexity of thorough verification. This book is an example of what can be possible when EDA companies and designers unite to solve an important problem for the semiconductor industry."
Warren Savage, President & CEO, IPextreme
"This book provides a thorough introduction to a design method which has the potential to have a profoundly positive impact on future chip developments - particularly by ‘taming the beast’ of verification. Cadence's clear commitment to the support and development of this new method based on open standards is heartening. Though a design engineer wishing to get on with implementing a TLM-driven design might want to skim through some of the history of design methods, the book's thorough presentation of the context in which TLM-driven design is proposed make it excellent source material for a design team wishing to make the case to management for the adoption of this new design method."
Colin Dente, CEO, Akya Ltd
"Transaction-level modeling with high-level synthesis has a potential to significantly improve the productivity of future IC designs. Describing designs in a high-level abstraction can enable faster design space exploration and improve the portability of Intellectual Property (IP) blocks by automating tedious and error-prone implementation processes. This book introduces a new hardware design methodology based on the high-level synthesis technology. The authors provide a comprehensive view on a whole system design process including verification and software development in addition to the hardware design, and show how these challenges can be addressed in the transaction-level design methodology using Cadence C-to-Silicon Compiler. To be able to achieve a high quality result from a high-level synthesis, a designer still needs to make architectural and mico-architectural decisions and guide the synthesis tool. For this purpose, the book also provides a good overview of the capabilities and limitations of today's high-level synthesis technologies and discusses the role of designers through design examples. This book will be a valuable resource for both students and industry engineers who want to be introduced to a design methodology based on the high-level synthesis."
G. Edward Suh, Assistant Professor, School of Electrical and Computer Engineering, Cornell University