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Cadence TLM-Driven Design and Verification Methodology 

Transaction-level modeling (TLM) takes design and verification to the next abstraction level, removing extraneous implementation detail so that engineers can focus on functionality. A TLM-driven methodology leverages high-level synthesis, metric-driven verification, and advanced ECO capabilities to enable: 10x faster IP reuse; 2x faster verification turnaround; 30-50% shorter debug cycle; and much broader micro-architecture exploration to optimize tradeoffs among latency/throughput, power consumption, and size.
Digital design productivity has benefited from regular leaps in the abstraction level of design entry—from SPICE-level to gate-level to RTL. Higher levels of abstraction remove implementation details so that designers can focus more on the functionality. But RTL contains implementation details such as logic depth between registers, structures for math logic, types of control logic, and even resource sharing.

The next abstraction level—transaction-level modeling (TLM)—removes all of this implementation detail so that design and verification can focus purely on functionality. Cadence offers the most complete solution for evolving your RTL-driven methodology to one driven by TLM. The advantages of the Cadence® TLM-driven design and verification methodology are compelling:

10x Faster Reuse
TLM-driven design and verification completely separates the design’s functionality, which is in SystemC®, from the details of how it will be implemented, which are contained in high-level synthesis constraints. This enables much easier reuse of IP across different types of applications that have different latency, size, and power requirements. Simply change the constraints and reuse the same design. This greatly reduces the amount of functional verification required.

2x Faster Verification Turnaround
Designing with TLM reduces the verification cycle even for new IP design. Because there are much fewer details to describe, fewer bugs get coded into the design, simulations run faster, and the source of bugs is much easier to track down. Customers using TLM for design and verification typically cite a 30-50% reduction in the overall verification-debug cycle. Because verification is often the bottleneck in the project schedule, using TLM can lead directly to schedule reductions.

Broader Micro-Architecture Exploration
Because TLM removes implementation details from the design, it facilitates much broader micro-architecture exploration in a shorter amount of time. This enables designers to find a more desirable balance of latency/throughput vs. power consumption vs. size.