Design and verification engineers can double the number of tests for their next project, but it may not be enough to verify their design. How do they know the “reusable” verification IP (VIP) is really ready for reuse? And with verification team spanning the globe, how will they create system tests efficiently? When every verification team is under pressure to maximize productivity, predictability, and quality, the verification methodology they choose is a critical decision.
The Open Verification Methodology (OVM) makes that decision easy. Its power to scale comes from the OVM verification component (OVC) which is an abstraction of the stimulus and monitoring needed to verify a design component, interface or protocols. It is architected for multiple verification languages and defined by a set of classes and methods in the OVM library. Since all OVCs follow this same structure—containing the sequence, monitor, and driver for a specific design interface—the entire verification ecosystem will easily understand how to reuse the OVCs they receive. OVM OVCs can also be integrated hierarchically and controlled by virtual sequences, enabling the verification environment to smoothly scale from block to system.
The OVM also provides built-in coverage collection, allowing the team’s verification environment to naturally integrate with the Cadence metric-driven verification
(MDV) flow. Used in conjunction with MDV, the OVM-based verification approach will enable team productivity, project predictability, and product quality needed to compress the Silicon Realization process.
- Abstraction scales from block to system and project to project
- Maximizes verification productivity, predictability, and quality—especially when used with metric-driven verification
- Reduces costs through its multi-language verification ecosystem