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Low-power verification flow 

Verify low-power design intent without disrupting the functional verification environment


Overview
Ever-growing design complexity and the challenges associated with power consumption are now affecting the ability to functionally verify designs. Techniques such as multi-supply voltage, power shut-off, and dynamic and adaptive voltage and frequency scaling all present new functional verification challenges. These low-power design techniques are typically not specified in the designer’s RTL, forcing complex adaptations to the customer’s verification environment.

The Cadence® low-power verification flow provides a seamless solution to these functional verification challenges. With native support for the Common Power Format (CPF), Cadence Incisive® verification technologies verify low-power intent with no disruption or modification to the functional verification environment. Low-power verification planning allows for the unique demands of low-power verification to be captured in an executable specification. Complex low-power design techniques are verified during functional verification, without requiring modifications to the design specification or test environment. Low-power functional verification metrics are collected and reported, and an easy-to-use graphical verification environment allows for quick debugging of issues related to errors in the low-power design intent.

Flow benefits
  • Verifies low-power design intent with no disruption or modification to the functional verification environment
  • Integrates low-power verification planning, coverage, and debugging with the functional verification environment
  • Native support for the Common Power Format guarantees that low-power intent gets verified as designed
Flow components
Resources