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Functional Verification 

One language can't solve all design and verification problems. Different teams use different languages to take advantage of the unique features each one provides. As a leader in open standards, Cadence is dedicated to providing continuous support for a variety of design and verification languages and implementation standards. To ensure unified standards for advanced design and verification, and to improve the process of turning specifications into fully implemented standards, Cadence is an active participant in multiple Accellera and IEEE standards committees.

Verilog is the incumbent de facto and IEEE standard (IEEE 1364-2001) for RTL design. In widespread use since the 1980s and supported by all major EDA vendors, Verilog is the basis for most logic synthesis tools and provides good support for ASIC design and verification of simple to moderately complex chips. The limitations of Verilog became apparent in the late 1990s as growing design complexity mandated better solutions for verification and higher abstraction levels for effective design and modeling. Verilog remains the language of choice for a broad cross-section of today's' designers who use it as an implementation language in a multi-language design and verification flow.

VHDL (IEEE 1076) enjoys a similar position to Verilog in terms of its scope and application to synthesizable design. Its appeal is rooted in its precise semantics and higher-level abstraction, and it is the language of choice for many design teams. VHDL continues to evolve; the latest update was standardized in 2008 (IEEE 1076-2008).

Rooted in the Verilog language, IEEE 1800 SystemVerilog adds the modern verification and design features needed for advanced node SoCs. This breadth expands the traditional use of Verilog for design and directed test throughout all aspects of silicon and system realization, from testbenches that drive SystemC TLM designs, to RTL testbench and formal verification, to hardware-based acceleration and more. The result is a virtuous circle that feeds new requirements into the IEEE SystemVerilog standard to improve the existing LRM, fill-in needed functionality, and expand it with new analog support.
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e language is an IEEE 1647 standard hardware verification language (HVL) that is tailored to implementing highly flexible and reusable verification testbenches, leading to a significant productivity improvement. e is one of the most mature verification languages, used by specialists for advanced verification. It is, therefore, the most mature in its coupling to overall verification methodology, technology, and verification IP (VIP), and it can scale to the most complex block/unit, chip, system, and project levels.
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Property Specific Language (PSL)
PSL (IEEE 1850) supports Verilog, VHDL, and SystemC languages. It includes multiple abstraction layers for assertion types ranging from low-level Boolean and temporal to higher-level modeling and verification. PSL continues to evolve; the latest update is the IEEE 1850-2010 standard.

SystemC language (IEEE 1666) is ideal for transaction-level modeling (TLM) and high-performance reference modeling. It can also be synthesized—a technical committee of the Accellera Systems Initiative is currently working on a standard language subset for synthesis. Testbenches for SystemC can be written in SystemC, but many product teams choose the Accellera Systems Initiative Universal Verification Methodology (UVM) SystemVerilog and/or e languages, enabling reuse of the tests at the next lower level of abstraction with Verilog and VHDL.

Globalization of design has increased the need to exchange intellectual property (IP) among groups in a single company and among companies in a design chain. The IEEE P1735 Recommended Practice for Encryption and Management of Electronic Design IP seeks to standardize the safe interchange of IP. It leverages public key encryption to enable multiple tools in the design chain, from multiple vendors, to operate on the IP.