Cadence Interconnect Validator verifies the interconnect fabrics that connect IP blocks and subsystems within an SoC. Whereas a principal aim of verification IP (VIP) is to verify that IP blocks follow a given communication protocol, Interconnect Validator verifies the correctness and completeness of data as it passes through the interconnect. Because it automates a critical, yet difficult and time-consuming task, Interonnect Validator greatly increases verification productivity at the subsystem and SoC levels.
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- AMBA protocol support: ACE, AXI4, AXI3, AHB and APB
- OCP 2.0 protocol support
- Supports verification at the subsystem and SoC levels
- Supports any number of master ports, slave ports, and interconnect
- Enables verification of hierarchal / cascaded fabrics
- Enables verification of non-standard interconnect
Interconnect Validator works in conjunction with VIP components to model and monitor all ports on an SoC’s interconnect. Sophisticated algorithms track data items as they are transported through the interconnect to their destinations. Arbitration of traffic is accounted for as well as data transformations such as upsizing, downsizing, and splitting.
Example SoC showing connection of VIP and Interconnect Validator
Interconnect Validator supports the verification of both non-coherent interconnect and coherent interconnect such as those based on ARM’s AMBA 4 AXI Coherency Extensions (ACE) specification.
Capabilities for Verifying Non-Coherent Interconnect
- Supports any number of masters and slaves
- Accommodates independent address forwarding for each master
- Handles data splitting, upsizing and downsizing
- Supports INCR, WRAP, and FIXED addressing modes
- Supports internal address ranges and unmapped access
- Supports transaction ordering
- Handles slave power-down, interconnect reset, and dynamic address forwarding
Additional Capabilities for Verifying Coherent Interconnect
- Supports any number of outer and inner domains
- Verifies snoop conversions, snoop propagation, and snoop filter operation
- Checks cross-cache line operations
- Supports DVM transactions
- Verifies barrier transactions
- Supports interconnect-initiated operations
Because interconnect behavior is always design-specific, Interconnect Validator can be extended and customized to enable design-specific checking. User-created rules can be added and standard protocol rules can be bypassed.
Interconnect Validator reduces verification effort by automatically creating a coverage model of all transactions exchanged between masters and slaves within an SoC. It includes a passive agent to monitor the SoC interconnect as well as an active agent to model interconnect behavior and enable SoC verification in cases where the interconnect design is not yet complete. Interconnect Validator supports both SystemVerilog and e
testbench languages and associated methodologies including UVM, OVM, VMM, and e