Cadence provides a metric-driven mixed-signal verification (MSV) flow for customers who employ digital-centric use models for high-performance mixed-signal verification to enable full-chip verification. The flow enables mixed-signal verification very close to digital speeds, and it can be used for high-volume, digital-centric nightly regressions runs.
The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly, one part would be treated as a black box and the two parts would be bolted together at the SoC level. But today’s mixed-signal designs have multiple feedback loops, complex modeling requirements, and higher performance targets, meaning it’s no longer possible to deconstruct designs into separate analog and digital functions.
Engineers need to embrace the digital centric metric-driven verification methodologies into their mixed signal verification flows.
Engineers also need an integrated mixed-signal verification environment that focuses on performance and reliability. Top-level SoC verification has become a critical challenge—and functional failures can result in costly design iterations and missed market windows.
Mixed-signal design and verification environments are not an entirely new ballgame. In the broader context, from an analog perspective, engineers have been doing mixed-signal design for years; however, it seems today that neither analog nor digital engineers are completely prepared to enter each others' areas of expertise. Analog engineers may shy from the complexity of SoC verification, and digital engineers may find the fuzziness of analog design disconcerting in the context of applications that must run on the chip. However, there’s simply no way to avoid this interaction. Functional integration is the key problem.
To address the functional integration problem at the SoC level, customers need to start with a verification plan. Verification planning is the process of using the spec to define what to check, not looking at the design and defining how to check. By planning what to check, the engineer makes sure that he/she covers all the features that are expected at the SoC level and not just what's designed into the block. This is a major failure area in MS SoCs in that the analog block is verified under different conditions at the SoC level than were verified at the block level. Verification planning is one of the key steps to managing the complexities involved in the Digital-centric Mixed Signal (DMS) verification flow. This translates into coverage, assertion based checking, score-boarding as well as the actual generation of appropriate stimuli for both digital and analog components. The planning process is always important for verification, but for MS it becomes critical. The sheer range of operating parameters and complex interaction of Analog/Digital units requires a clear definition of relevant metrics defined and measured for both Analog & Digital design units. Traditionally, there has been very little functional coverage collected from within the analog domain. Now, it is possible to include analog parameters as part of the coverage models when using the DMS verification flow. Key metrics and targets for functional completeness of the DMS effort are captured in an executable spec often called the vPlan which attaches itself to the verification environment. As simulations are run, the coverage information is collected and annotated into the vPlan to give a graphical representation of the percentage coverage you have achieved.
The Cadence® MSV flow leverages real number-modeling (RNM) so that users can perform top-level verification of their analog or mixed-signal designs using discretely simulated real number models. Because these Real/Wreal models are the digital equivalent model of an analog block, engineers can verify a full-chip SoC using only a digital simulator. This eliminates relatively slow analog simulation and convergence issues, allowing for nightly regression runs of the mixed-signal SoC. RNM can also integrate with other advanced verification technologies, such as assertion-based verification and metric-driven verification without having to interface with the analog engine or defining new semantics to deal with analog values. Using the Cadence MSV flow, engineers can greatly enhance the top-level verification performance of the overall verification process.
Improves time to market
- Overnight mixed-signal regression runs ensure the SoC meets the spec
- Ensures product quality
- Leverages high-performance, real-number modeling
- Performs top-level, metric-driven mixed-signal SoC verification
- Finds and helps fix errors much earlier in the design cycle by performing full-chip functional verification
- Eliminates convergence issues with digital-speed performance
- Easily and accurately ports models between Virtuoso® and Incisive® environments
- Enables top-level SoC verification