Methodology documentation and detailed examples within the same environment
The Cadence® Incisive® Plan-to-Closure Methodology and Incisive Verification Kits have been merged into a single comprehensive deliverable. The objective of the merge was to enable both methodology documentation and detailed examples to be shown from within the same environment, called a kit. Both methodology content and kit content are available to Incisive users in the KITSOCV release: Incisive Verification Kits with Plan-to-Closure Methodology.
Incisive Verification Kits with Plan-to-Closure Methodology automates and eases the adoption of reusable advanced verification techniques, increasing productivity and predictability. Kits implement the Plan-to-Closure Methodology using an interactive flow-based approach.
For an overview of Incisive Verification Kits, watch the
video.
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There are two levels of Incisive Verification Kits:
IP Verification Kit for IP and block-level verification
This environment is designed to run with Incisive Enterprise Simulator XL, Incisive Formal Verifier, and Incisive Enterprise Manager. It is freely licensed to all Incisive Enterprise Simulator XL and Incisive Formal Verifier users. The kit contains advanced verification for block- and IP-level flows in both SystemVerilog and e (OVM and eRM), formal analysis, and verification planning and management. It includes all current and relevant Plan-to-Closure Methodology documentation. The verification examples are based on a standard Verilog® UART design.
SoC Verification Kit for chip- and system-level verification
This environment is designed to run with Incisive Enterprise Simulator XL, Incisive Formal Verifier, Incisive Enterprise Manager, and Incisive Software Extensions. Because this kit includes third-party IP, it requires a separate user-signed license agreement. It contains advanced verification for chip- and system-level flows in both e and SystemVerilog (eRM and OVM), formal analysis, hardware/software co-verification, and verification planning and management. It includes all current and relevant Plan-to-Closure Methodology documentation. The verification examples are based on a typical and representative wireless ARM-based SoC design.
Use the links below to find information previously housed on the MyIPCM site.
Quick Links
Incisive Verification Kits with Plan-to-Closure Methodology
Verification IP
Related Links