Leveraging design intent for faster, higher quality design verification
Assertion-based verification is one aspect of any complete SoC or Silicon Realization flow. Assertions capture specifications and design intent in an executable form. They act as monitors during simulation, detecting errors close to their source and reporting both errors and coverage information. Assertions also enable formal analysis, which can provide exhaustive verification of blocks and interfaces. Through the use of assertions, verification can start earlier, design and verification teams can detect and remove bugs faster, and designers can incorporate their intent into the design code to minimize integration issues later on.
The Cadence® assertion-based verification (ABV) flow includes support for IEEE 1800 SystemVerilog Assertions (SVA) in SystemVerilog code, support for IEEE 1850 Property Specification Language (PSL) assertions in SystemVerilog, Verilog®, VHDL, and SystemC® code, and support for IEEE 1647 e verification language assertions in e code. The Cadence Incisive® Assertion Library provides a set of assertion modules for many standard functions that enable the adoption of an ABV flow without learning a new language, including full support for the Accellera Open Verification Library (OVL) definition.
Supporting these assertion capabilities are the entire set of Incisive verification technologies, including Incisive Formal Verifier, Incisive Enterprise Verifier, Incisive Enterprise Simulator-XL, Cadence Palladium® accelerators/emulators, and Incisive Enterprise Manager for verification planning and management.
Coverage technologies like Incisive Enterprise Manager focus on tracking the specified behavior leveraged by the assertion languages. All coverage points are monitored during simulation and a count is provided that shows the number of times the behavior evaluated was true. Incisive Enterprise Manager can provide an aggregate view across simulation tests as well as across technologies for functional coverage and failure analysis, such as Incisive Formal Verifier and Incisive Enterprise Verifier.
Incisive Formal Verifier can be used for exhaustive verification of design correctness with respect to assertion specifications. It uses these same assertions to exhaustively prove that an “asserted” behavior is true under all combinations (and sequences) of input stimulus that is “assumed” valid. A Palladium accelerator treats assertions the same way a software-based simulator does—when the input stimulus violates the expressed behavior, an error message is reported.
Building on the combination of Incisive Formal Verifier, Incisive Enterprise Simulator-XL, and metric-driven verification technology, Incisive Enterprise Verifier combines the strengths of each technology in unique, mutually reinforcing ways to enhance the scalability and effectiveness of the analysis, as well as contribute a wealth of coverage metrics to further accelerate metric-driven SoC and Silicon Realization
- Captures design intent and travels with the design
- Detects errors close to their source, resulting in faster defect removal
- Provides control-oriented functional coverage information
- Enables formal analysis and a combined formal/simulation methodology