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Functional Verification 

AMD
AMD
Alex Starr
Alex Starr, Hardware Emulation Architect at AMD, highlights the unique capabilities of Palladium XP and in-circuit acceleration

AMD
AMD
Bryan Sniderman, Verification Architect for AMD, introduces the UVM Multilanguage (ML) Open Architecture to simplify verification IP (VIP) reuse.

3Leaf Systems
Design Challenge
Shorten the overall design and verification process time
Incorporate a formal verification strategy into the existing flow to increase the quality of results over simulation

Cadence Solution
Introduced the design team to a formal verification strategy as part of the Assertion-based Verification flow that allowed them to accelerate ramp up and achieve desired results for both quality and efficiency
 Read Full story »

Agere Systems
Design Challenge
Adopt a new verification environment to enable hardware/software co-verification
Speed development time for 6-million-gate Link Layer Processor

Cadence Solution
Demonstrated the power of the Cadence Palladium® accelerator/ emulator by bringing up a new verification environment in only two weeks
Success of initial project convinced Agere to choose the Incisive Palladium II system for future designs
 Read Full story»

Anchor Bay
Design Challenge
Larger chips but shorter design cycles
Integrating an entire transceiver supporting multiple standards onto a single SoC

Cadence Solution
Cadence Incisive Xtreme III boosts design team verification productivity with instant "hot swap" among simulation, acceleration, and emulation
 Read Full story»

ClearSpeed
Design Challenge
Achieve better compliance measurement of verification processes
Reach coverage goals easier and faster to meet aggressive time-tomarket schedules
Improve project management capabilities

Cadence Solution
The Cadence Compliance Management System provided ClearSpeed a simple, automated path to complete compliance verification
Read Full story »

Fujitsu Microelectronics
Design Challenge
Align power design around CPF with accurate simulation
Move to smaller geometries
Reduce design time and improve QoS

Cadence Solution
Integrated, proven design solution leverages success in new applications
Accurate verification of final design improves silicon
 Read Full story»

iVivity
Design Challenge
Bring to market iDiSX, a high-performance, multi-core SoC that combines high integration with low power to accelerate the development of intelligent storage systems
Leverage proven IP to reduce risk, identify bugs, and accelerate project completion

Cadence Solution
The PCI Express IP solution, a plug-and-play component incorporating automatic stimulus generation, assertion checking, and functional coverage at the module, chip, and system levels
 Read full story »

LSI Corporation
Business Challenges
Establish a proven mixed-signal methodology to verify analog IP for a mixed-signal chip
Produce a high-quality product in a short time-to-market window
Design Challenges
Upgrade ad-hoc, manual verification methodology for analog IP
Leverage current, optimal verification flow for digital IP
Cadence Solutions
Incisive Enterprise Simulator
Incisive Enterprise Manager
Incisive Enterprise Specman Elite Testbench
Virtuoso AMS Designer
Virtuoso Schematic Editor
Virtuoso Analog Design Environment
Customer Support
Results
Established a methodology that can be extended to analog verification
Expanded analog design verification coverage and improved product quality
Met design and performance specifications
 Read Full story»

Newport Media
Design Challenge
Expose hard-to-find bugs early in the design cycle of AHB master/ slave to verify protocol compliance
Write more extensive tests to uncover and explore corner cases

Cadence Solution
The Cadence Incisive Formal Verifier solution including Assertion Based Verification IP (VIP) were used to improve the productivity and quality of functional verification earlier in the design and verification process
 Read full story »

Nufront
Business Challenges
Quickly roll out a third-generation dualcore Cortex-A9 mobile computing chip without sacrificing quality
Enable customers to speed up product launches and win more business
Design Challenges
Design a complex chip with 12M gates
Comply with strict mobile-computing platform requirements
Achieve low levels of power consumption and a high level of performance
Cadence Solutions
Palladium XP Verification Computing Platform
Incisive Enterprise Manager
Palladium XP Dynamic Power Analysis
SpeedBridge rate adapters
Results
Sped up simulation goals by approximately 1,000x
Increased productivity while meeting stringent quality requirements
 Read Full story»

NVIDIA
Narendra Konda
NVIDIA
Narendra Konda, Director of Hardware Engineering at NVIDIA, outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, develop app-ready systems more quickly, and ultimately improve the overall quality and competitiveness of their products.

Philips
Design Challenge
Adopt a new process that would allow the team to achieve higher productivity without disrupting their existing design flow

Cadence Solution
Deployed the Cadence Incisive® Xtreme® Server, an easy-to-use solution that integrated seamlessly into the team's existing SoC design flow
 Read full story »

QLogic
Business Challenges
Quickly produce a sophisticated new network switch to capture market share
Design Challenges
Ensure success of complex ASIC design with system-level verification
Cadence Solutions
Palladium XP Verification Computing Platform
Customer Support
Results
Achieved verification of an ASIC design at the system level, earlier in the design cycle and faster than in previous ASIC verification projects
Reduced verification time by 50% compared to previous, less-complex switches
 Read Full story»

Renesas
Design Challenge
Migrate Renesas engineers to a new system-level design methodology based on next-generation high-level synthesis (HLS)
Demonstrate significant productivity improvements in creation and retargeting of RTL designs

Cadence Solution
Two-year R&D partnership with Renesas engineers to adapt HLS technology developed at Cadence for production usage at Renesas
Next-generation Cadence HLS technology tailored and refined for real production based on feedback from Renesas engineers
Comprehensive design and verification methodologies/flows specified by and developed with Renesas engineers in order to integrate HLS with other Renesas production design flows
 Read Full story»

RivieraWaves
Business Challenge
  • Produce highly differentiated low-power Bluetooth 4.1 IP in aggressive timeframes
Design Challenges
  • Migrate from OVM to UVM for next-generation Bluetooth 4.1 IP design verification
  • Find bugs faster and sooner
  • Effectively manage new, complex IP challenges
  • Meet robustness goals while achieving new levels of efficiency
Cadence Solutions
  • Incisive Enterprise Simulator
    • SimVision
    • Incisive Metric Center
  • Incisive Enterprise Manager
Results
  • Reduced the debug cycle in the overall verification project by 30%
  • Reduced the debug cycle in the overall verification project by 30%
  • Quickly and easily migrated from OVM to UVM environment
  • Achieved faster IP delivery to customers, enabling faster time to market
  • Met efficiency goals
 Read full story»

Samsung
Business Challenges
Deliver new SSD products to market on time
Expand market share and grow into new applications
Design Challenges
Complete verification efficiently for new SSD products
Enable early firmware and driver integration, and debug, prior to FPGA prototype availability
Cadence Solutions
Palladium XP with simulation acceleration use model
Accelerated VIP for PCI Express
Results
Increased validation speed multiple hundreds of times compared to simulation
Increased validation team productivity by 100%
 Read Full story»

Siemens Healthcare
Business Challenge
New image-chain platform design demanded the highest levels of quality, reliability, and flexibility, which would require a more effective verification environment
Design Challenges
Existing verification flow hampered productivity
Incomplete language implementation and immature tools
Repeated recodes
Lack of automation and reuse
Cadence Solutions
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Manager
Customer Support
Results
Increased verification productivity by 30% compared to previous methodology
Delivered reliable platform on time, with no unexpected delays
Achieved flexibility for future expansion
 Read full story»

Siemens
Design Challenge
Build an all-encompassing chip-level verification plan over the entire functionality of the ASIC, including both hardware and software, that addresses real-life use cases and user scenarios
Reduce overall project time
Develop a flexible, trustworthy verification plan to stay on track, manage progress, and automate coverage collection to address unforeseen design changes
Integrate formal analysis technology into the verification flow

Cadence Solution
Cadence Incisive Enterprise Manager
Cadence Incisive Enterprise Specman Elite Testbench
Cadence Incisive Formal Verifier
Cadence Incisive Enterprise Simulator
 Read Full story»

Sigma
Design Challenge
Accelerate verification schedules and provide firmware engineers with earlier access to a hardware platform to verify their designs in a pre-silicon environment
Establish a methodology that can be easily integrated into existing processes

Cadence Solution
Palladium series of hardware assisted verification technologies with both in-circuit emulation and transaction-based acceleration capabilities
 Read Full story»

Silicon Laboratories
Design Challenge
Full-chip verification was much too slow with regard to integrating the analog and digital content at the full chip level
Verification productivity must be improved by allowing users to begin the digital verification effort much sooner in the overall process

Cadence Solution
Cadence Incisive Enterprise Simulator running the Digital Mixed Signal option
Cadence Mixed-Signal Solution allows users to seamlessly connect Real Value Models to the digital content
 Read Full story»

STMicroelectronics
Design Challenge
Verify a 100-million-transistor IC on a tight schedule using existing verification environment

Cadence Solution
HW-based verification system
 Read full story »

STMicroelectronics
Business Challenges
Increasing time-to-market pressure for high-quality microcontrollers
Design Challenges
Needed an enhanced, accelerated methodology to verify digital IP components
Required a more effective verification reuse methodology
Required 100% code coverage, 100% functional coverage, and 100% of tests passing without any manual checks
Cadence Solutions
Incisive Enterprise Simulator
Incisive Enterprise Specman Elite Testbench
Incisive SimVision
Incisive Enterprise Verifier
Incisive Enterprise Manager
Incisive Verification IP (VIP)
Accellera Systems Initiative Universal Verification Methodology (UVM)
Results
Reduced the average verification effort for a new digital IP from 35 weeks to 25 weeks, speeding time to market
Achieved zero-defect delivery
Met stringent quality goals early in verification process
 Read Full story»

STMicroelectronics
Business Challenge
  • Achieve faster debug of RTL data cache flow
  • Quickly gain familiarity with new testbench for enhanced productivity
Design Challenges
  • Learn testbench environment and manage debug process independently after support from testbench developer ended
  • Detect and resolve bugs faster and earlier in the process
Cadence Solutions
  • Incisive Debug Analyzer
  • Incisive Specman Elite Testbench
  • Incisive Enterprise Simulator
  • SimVision
Results
  • Saved 2 months of debugging time
  • Enhanced team productivity with easy-to-use debug tool
 Read full story»

STMicroelectronics
Laurent Mailet-Contoz
STMicroelectronics
Laurent Mailet-Contoz, Project Leader from STMicroelectronics uses the Incisive verification platform at the transaction level to reduce their design cycle and help the company to be the first to new markets.

Sun Microsystems
Design Challenge
Develop the highest throughput and most eco-responsible processor available
Employ a verification platform that could eliminate costly respins and accelerate project completion

Cadence Solution
Seamlessly integrated simulation, acceleration, and in-circuit emulation into a single verification environment
 Read full story »

Sun Microsystems
Jai Kumar
Sun Microsystems
Jai Kumar, Verification Technologist from Sun Microsystems shared his verification experience of advanced development of UltraSPARC processors with Cadence Incisive Xtreme series.

Texas Instruments
Business Challenge
Short time-to-market window for complex mixed-signal design verification
Design Challenges
High-performance, ultra low-power features in close interaction with core analog functional blocks at the SoC level
High-volume product
Functional failures would lead to costly design iterations
Cadence Solutions
Digital-centric mixed-signal verification flow
Incisive Enterprise Simulator Digital/Mixed-Signal (DMS) Option
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Manager
Virtuoso AMS Designer with flexible analog simulation
Virtuoso Accelerated Parallel Simulator – XL
Customer Support
Results
300x faster verification vs. mixed-signal simulation at the transistor level
Improved time to market and product quality with mixed-signal regression runs
Fewer re-spins with high-performance, real-number modeling and top-level, metric-driven mixed-signal SoC verification
Earlier detection and correction of errors
10x cycle-time improvement in mixed-signal verification
 Read Full story»

Texas Instruments
Business Challenges
Deliver the best application processor with optimal performance, power consumption, and thermal conditions
Limit power consumption within two watts
Design Challenges
Provide accurate power estimation based on real use cases
Develop a methodology and a power dashboard, and continually track power updates
Achieve close correlation between an architect’s power estimation and actual silicon measurement
Cadence Solutions
Palladium XP Dynamic Power Analysis
Encounter Power System
Results
Power estimation and actual silicon measurement at 96% accuracy
Detected unexpected power peaks and resolved design to lower power consumption
 Read Full story»

Unisys
Design Challenge
Expose hard-to-find bugs early in the design cycle of the complex ES7000 Real-Time Capacity Server Series
Verify design blocks prior to testbench simulation for faster time-to-market

Cadence Solution
The Cadence Incisive Formal Verifier technology as part an assertion-based verification flow was incorporated into the production design flow complementing Incisive Design Team Simulation and Incisive Palladium Emulation
Design with Verification in mind started with logic design teams early in the project cycle minimizing lengthy tail-end functional iterations
Productivity and product quality were dramatically increased
 Read full story »

UPEK
Design Challenge
Speed the design cycle
Incorporate an assertion-based verification methodology (across formal analysis and simulation) into an existing design and verification flow

Cadence Solution
Address key verification issues up front in the design
Add Incisive Formal Verifier (including Incisive Design Team Simulator) to UPEK's existing flow
 Read full story »

Xilinx
Business Challenges
Shrink turnaround time for IP design testing
Design Challenges
Accommodate designs with multiple, multivalue parameters
Eliminate parameter set repetition
Avoid redundant test suite regressions
Cadence Solutions
Cadence Specman within the Incisive Enterprise Simulator
Results
Enhanced parameter generation with support for both exhaustive and randomized sets
Reduced simulation runtimes by 20% to 30%
Increased productivity for hard and soft IP development
Greater overall IP quality
 Read Full story»

Samsung
Business Challenge
Reduce regression turnaround time (TAT) from five days to one day for register-transfer level (RTL), and from five days to two days for gate-level simulation (GLS)
Design Challenges
The application processor system on chip (SoC) would quickly grow to 150 million gates and beyond
Logic simulation runtime takes longer and consumes more memory with each design generation
Cadence Solutions
Incisive Enterprise Simulator
Incisive SimVision
Incisive Enterprise Manager
Incisive Verification IP (VIP)
Accellera’s Universal Verification Methodology (UVM)
Results
Reduced RTL regression time by 80% and GLS by 60%
Achieved 1.5x speed increase for Standard Delay Format (SDF) GLS and 2.2x speed increase for zero-delay GLS
Reduced long-running RTL simulation time from 100 hours to 4 hours
Reduced number of simulation builds from 315 to 20, saving 96% of disk space and 42% of total regression runtime
 Read Full story»

Duolog
David Murray
Duolog
David Murray, CTO at Duolog, discusses collaborating with Cadence to help customers address SoC integration and verification.

Freescale Semiconductor
Freescale Semiconductor
Wai-Chee Wong
Wai-Chee Wong, Senior Member of Technical Staff at Freescale Semiconductor, details how Palladium XP helps speed their verification effort by 10,000x over simulation.

Freescale Semiconductor
Anis Jarrar
Freescale Semiconductor
Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.

Freescale Semiconductor
Angela Liang
Freescale Semiconductor
Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence Low Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.

Fujitsu Semiconductor Europe GmbH
Raimund Soenning
Fujitsu Semiconductor Europe GmbH
Raimund Soenning, Manager at Fujitsu Semiconductor Europe GmbH describes how they leverage the Cadence functional verification methodology to help develop large SoCs in the automotive industry.

IBM
IBM
Nancy Pratt
 Nancy Pratt, BIST Verification Lead at IBM, details the use of Cadence Verification tools to help streamline and provide more detailed reports, improve planning and increase scheduled adherence.

NVIDIA
Narendra Konda
NVIDIA
Narendra Konda, Director, HW Engineering at NVIDIA, discusses leveraging Palladium XP and the Rapid Prototyping Platform to integrate complex hardware and software designs.

S3
S3
Flavio Cali
Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.

STMicroelectronics
Abhishek Jain
STMicroelectronics
Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification.

Technical University of Braunschweig
Challenges
Prepare students for workforce by teaching with powerful electronic design automation (EDA) technologies
Cultivate relationships with educators and corporations to further academic research in low-power digital design
Cadence Solutions
Cadence Academic Network
Incisive Unified Simulator
Encounter RTL Compiler
Encounter Digital Implementation System
3D Design Viewer
C-to-Silicon Compiler
Results
Students earn internships and jobs at leading technology companies with a strong presence in Europe
TUBS participates in publicly funded research projects involving low-power digital design
 Read Full story»