3Leaf Networks 3Leaf Networks Improves Quality, Shortens Cycle By Adding Cadence Incisive Formal Verifier to Their System Verification Process Agere Systems Agere Saves Six Months in Project Schedule using Cadence Palladium Accelerator/Emulator Anchor Bay Incisive Xtreme III Accelerates Simulation While Preserving Anchor Bay's Familiar Verification Environment ClearSpeed Cadence Compliance Management System Enables ClearSpeed to Reach Coverage Goals Faster Fujitsu Network Technologies Incisive Platform Accelerates Newly Adopted SystemC Design Flow IBM Incisive Palladium Accelerator/Emulator Shortens Project Cycle By 11 Weeks iVivity Incisive Verification IP Reduces Risk, Increases Productivity for iVivity Layer N Networks Incisive and Encounter platforms enable front-to-back complex SoC design Magis Networks Cadence Incisive unified simulator helps achieve one-pass success Newport Media Newport Media Pinpoints Design Bugs Earlier with Cadence Assertion Based VIP and Incisive Formal Verifier NVIDIA Corporation Incisive Palladium Accelerator/Emulator gives 9x Boost in Productivity Philips Philips Streamlines Complex SoC Development Process Using Cadence Incisive Xtreme Verification System S3 S3 Chooses Cadence for Verification of Multi-million-gate, 3D Graphic Design sci-worx sci-worx Significantly Improves Productivity by Replacing FPGA Prototyping with Cadence Incisive Palladium Accelerator/Emulator STMicroelectronics ST Speeds Verification Process for Remote Divisions using Palladium Accelerator/Emulator STMicroelectronics STMicroelectronics Employs Xtreme Verification and Significantly Shortens Simulation Cycles of Extremely Advanced Telecom Chip Sun Microsystems Incisive Xtreme Server Helps Speed the Completion of Breakthrough Processor Technology Unisys Design with Verification Flow Starting with Incisive Formal Verifier Boosts Productivity and ASIC Quality at Unisys UPEK UPEK Increases Design Productivity using Cadence Incisive Formal Verifier Archived success stories>>
Videos
Chris Malachowsky nVidia nVidia VP of Engineering Chris Malachowsky talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help nVidia get results. RealMedia:Low (35K) |
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Jai Kumar Verification Technologist from Sun Microsystems Jai Kumar, Verification Technologist from Sun Microsystems shared his verification experience of advanced development of UltraSPARC processors with Cadence Incisive Xtreme series. RealMedia:Low (35K) |
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Laurent Mailet-Contoz Project Leader, STMicroelectronics ST uses Incisive verification platform at the transaction level to reduce their design cycle and help the company to be the first to new markets. RealMedia:Low (35K) |
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Patrick Scheer Philips The Palladium™ accelerator/emulator helps Philips Semiconductors speed up their verification by 57X. RealMedia:Low (35K) |
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Tim Richardson Micro Linear CEO Micro Linear and Cadence collaborate on successful next-generation RF transceiver design. RealMedia:Low (35K) |
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