|
|
 |
 |
|
|
|
|
|
|
Home > Products > Incisive functional verification > Products > Simulation
|
|
 |
Incisive Simulation
Simulation is a key component of Cadence® Incisive® functional verification technology. With native mixed-language support, dynamic assertion checking, transaction-level support, HDL analysis, and a complete debug environment, Incisive simulation verifies nanometer-scale ICs with speed and efficiency.
Cadence offers three Incisive simulators, each tailored to specific needs: the Enterprise Simulator for complex system development and verification; the Design Team Simulator for full multi-language simulation including SystemVerilog; and the HDL Simulator for basic RTL simulation. With Incisive simulation, engineers can take the risk out of verification while improving productivity, project predictability, and product quality.
Incisive Simulation is compatible with the Open
Verification Methodology (OVM) and the
e Reuse Methodology (eRM).
Key benefits
Incisive Enterprise Simulator | Blends leading-edge verification process automation (VPA) technology, high-performance engines, and advanced debug capabilities to simplify and accelerate the workflow | | Provides advanced testbench automation including aspect-oriented programming, the ability to build scenarios of likely tests, and an "infinity minus" approach to test generation | | Built-in verification manager drives the verification process right from the planning stage with an automatically backannotated vPlan executable specification | | Supports any mix of IEEE-standard languages: Verilog®, VHDL, SystemVerilog, e, SystemC®, | | Supports the comprehensive Plan-to-Closure Methodology with metric planning and management via vPlan executable specifications, and e language and SystemVerilog class-based reuse features | | Offers an integrated graphical user interface (SimVision) | | Provides comprehensive coverage capabilities including code, functional, and transactional, plus automatic data and assertion checking | | Includes new productivity components: Scenario Builder to create reusable sequences and multi-channel test cases on top of an e verification environment (no training required); Verification Builder to rapidly configure existing Universal Verification Components (UVCs) or quickly construct all-new UVCs; and eAnalyzer for GUI-based static analysis and methodology enforcement | | Part of the Incisive Enterprise family of products |
Incisive Design Team Simulator | Supports Verilog, VHDL, SystemVerilog, SystemC, PSL, and SVA | | Offers an integrated graphical user interface (SimVision) | | Provides comprehensive coverage capabilities including code, functional, and transactional | | Provides comprehensive HDL analysis capabilities | | VPA enabled to transfer coverage data to verification management tools | | Part of the Incisive Design Team family of products |
Incisive HDL Simulator | Supports Verilog, VHDL, and the designer portion of SystemVerilog | | Offers an integrated graphical user interface (SimVision) | | Provides integrated code coverage | | Easily upgrades to the Design Team Simulator or the Enterprise Simulator | | Part of the Incisive HDL family of products |
| The three simulators of the Incisive platform |
| | |
|
|
|
|
|
|
