Cadence Kits
Incisive functional verification
PRODUCTS
Verification management
Formal analysis
Testbench automation
Simulation
Acceleration/emulation
Analog-mixed signal
Verification IP
Plan-to-Closure Methodology
DESIGN TASKS
Enterprise system-level verification
Transaction-based system verification
Transaction-based acceleration
Assertion-based verification
Building an emulation environment
Verification Methodology for SOC's
Encounter digital IC design
Virtuoso custom design
Allegro IC-PKG-PCB co-design
OrCAD PCB design
System-in-package design
Design for manufacturing
IP catalog
Print-friendly version

Functional verification News and Events

This page contains technical information related to Functional verification, including press releases, articles and events.

For the latest news and events, please subscribe to the Incisive verification newsletter.

Press releases



04/15/08IDT Uses Cadence Encounter Conformal Constraint Designer to Accelerate Time To Market
04/02/08PLX Technology Adopts Cadence Incisive Palladium II Accelerator/Emulator for Full System Verification
03/25/08Cadence Encounter Conformal ECO Designer Improves Logic Designers' Productivity
03/21/08Sunplus Selects Cadence Incisive Xtreme to Meet Faster Time to Market by Achieving Orders of Magnitude Performance Gain in Simulation Acceleration
02/14/08Cadence and Mentor Enhance Open Verification Methodology and Expand Community Activities to Support Rapidly Growing User Base
02/06/08Cadence Enables STMicroelectronics to Verify Latest Multimedia Designs for Wireless Devices
morepress releases

Third-party press releases



08/27/07Cadence Selects Wipro-New Logic's Wireless LAN IP for its SoC Functional Verification Kit
08/27/07Cadence Selects Chipidea's USB 2.0 IP For Its SoC Functional Verification Kit
07/09/07OCP-IP Announces Support for Cadence's Assertion Based OCP Protocol Verification IP
allthird-party press releases

Articles



04/28/08New standards effort targets verification IP interoperability
04/28/08Accommodating Change
04/22/08What floorplan information is needed for synthesis
04/17/08Cadence Announces Reentry Into Upstream Design in Japan
04/17/08Validating false path timing exceptions
more articles