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Home > Products > Incisive functional verification > Products > Formal analysis
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Incisive Formal Analysis
Incisive® Formal Analysis shortens design and verification time while improving design quality. It provides a formal means of verifying RTL functional correctness with assertions, without the need of testbench simulation, and is an effective means of providing predictable, fast RTL block bring-up. A key part of the Incisive verification platform's complete assertion-based verification (ABV) offering, formal analysis does not require a set of test vectors, which means functional bugs can be detected months before testbench development and simulation.
The Incisive Formal Verifier is an integral part of the Incisive Design Team family, and enables block level verification for design and verification specialists as part of the Incisive Enterprise family.
The Incisive® Formal Verifier enables you to improve the productivity and quality of functional verification earlier in the design and verification process. Production schedules are significantly reduced because design engineers can begin verification as the chips are being designed, findings functional bugs more efficiently.
Incisive Formal Verifier provides you with a complete environment, including Incisive language front-end, Incisive analysis and debug, as well as a common set of assertions that can be used in simulation and acceleration/emulation
Key benefits
 | Enables verification to start months earlier than traditional verification as there is no need for testbench | | Exposes corner-case bugs that are difficult or even impossible to find using simulation, acceleration, or emulation | | Allows designers to converge quickly to stable and functionally correct RTL | | Offers better predictability for front-end designers, resulting in shorter block integration time | | Broad support for design languages including Verilog, SystemVerilog, VHDL and mixed language environments | | Broad support for assertions written in PSL and SystemVerilog Assertions (SVA), and using the OVL and Incisive Assertion Library | | Automatic assertion extraction for common assertions such as those for FSMs, deadcoe, etc | | Provides effective and advanced debug and analysis environment including linting, waveforms, and coverage | | Supports a comprehensive Assertion-Based methodology aimed at maximizing quality and productivity gains | | Works synergistically with the Incisive Design Team Simulator and Incisive Enterprise Simulator, and can also be deployed in flows using third-party simulators |
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Incisive formal verification flow
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Cadence provides a complete, well-integrated solution
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