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Home > Products > Incisive functional verification > Products > Incisive Enterprise family
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Incisive Enterprise family
The Incisive Enterprise family provides verification process automation from plan to closure, reducing the risk of failure by maximizing team productivity, design quality and project predictability. Optimized for projects with specialized teams of engineers, Incisive Enterprise family combines best-in-class tools, standard languages, pre-packaged methodologies and customized verification environments tailored to the needs of each engineering team within a project: RTL designers, verification engineers, system-level specialists, software engineers, and project managers.
The Incisive Enterprise family includes the following products and methodologies:
| Incisive Enterprise family |
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The Incisive Enterprise Simulator utilizes a single-kernel architecture for efficient multi-language verification of models and testbenches based on Verilog, SystemVerilog, VHDL, SystemC, PSL, and OVL. A direct kernel interface (DKI) to e also provides high-performance simulation with e-based testbenches. HDL analysis, integrated code coverage, and powerful interactive debug with specialized views complete this verification management solution.
Incisive Enterprise Manager is central to the plan-to-closure methodology and guides the entire team through the verification process from initial planning to final closure. It automatically collects and analyzes metric data from the entire Incisive Enterprise family — giving managers the accurate view of project status necessary to prioritize resources for the greatest impact on closure. Using Incisive Enterprise Manager, the entire team can benefit from a faster, more predictable path to verification closure.
The Incisive Palladium series of accelerator/emulators adds high-performance, system-level acceleration and emulation — boosting verification performance throughout the design cycle — by as much as 1,000,000 times.
The Incisive Enterprise Family can further improve verification productivity with formal analysis and reusable verification IP. Additional products include: Incisive Formal Verifier and the Incisive Verification IP (VIP) library.
Key benefits
 | Provides a metric-driven methodology that increases the predictability of verification closure and avoids project delays due to residual bugs discovered late in the process | | Provides a fully integrated, multi-language environment, with specialized views, that meets the needs of the entire project team | | Single-kernel multi-language simulation architecture with direct kernel interface to e-based testbenches for highest performance |
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