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Home > Products > Incisive functional verification > Products > Incisive Design Team family
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Incisive Design Team Family
The Incisive® Design Team family enables design engineers to thoroughly verify their RTL block and chip-level designs without the risk of destabilizing their existing verification process. The solution combines best-in-class tools, standard languages, simulation acceleration, and pre-packaged methodologies optimized for the needs of RTL design teams.
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The solution is based on the following new and existing products all coupled with a plan-to-closure methodology centered on an incremental approach to assertions and test bench automation.
| Incisive Design Team family |
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A key component of the product family is the Incisive Design Team Simulator, which utilizes single-kernel architecture for efficient verification of models and testbenches based on Verilog®, SystemVerilog, VHDL, SystemC®, PSL, and OVL. HDL analysis, integrated code coverage and powerful interactive debug complete this simulation solution.
Incisive Design Team Manager is central to the plan-to-closure methodology and guides the designer through the verification process from initial assertion and test planning to failure analysis and RTL closure. It collects and analyzes coverage data from the other tools in the family and helps analyze failures and prioritize resources where they will have the greatest impact on realizing closure. Using the Incisive Design Team Manager, the design team can benefit from a faster and much more predictable verification process.
The Incisive Design Team Formal Verifier is optimized for assertion-based static analysis, and enables design teams to start their verification effort very early in the design process.
Add to this the powerful capabilities of the Incisive Design Team Xtreme Server, which boost verification performance by enabling a smooth flow from the Incisive Design Team Simulator to hardware-assisted, high-performance verification.
Cadence's comprehensive plan-to-closure methodology is tailored specifically to the needs of design teams. It includes a guide for creating effective SystemVerilog testbenches, verification acceleration, and an incremental approach to assertion-based verification that encompasses both simulation and formal techniques.
The Incisive Design Team family of products enables an incremental approach to the adoption of powerful SystemVerilog and/or PSL-based solutions that minimize the risk of the new design flow. It complements the capabilities of the Incisive Enterprise Verification family of products, which allow design and verification teams working on larger, multi-specialist project teams to link into a broader verification process spanning block, chip, and system levels.
The Incisive Design Team family is compatible with the
Open Verification Methodology (OVM).
Key benefits
 | Dramatically improves the productivity of design teams tasked with verification | | Reduces the learning curve associated with SystemVerilog testbenches and assertion-based verification | | Improves the quality of RTL designs based on resource optimization and objective coverage metrics | | Increases the predictability of verification closure and avoids project delays due to residual bugs discovered late in the process | | Shortens regression test turnaround time with acceleration, which further helps design teams to identify problems early in the design cycle |
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