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Home > Products > Incisive functional verification > Products > Analog-mixed signal
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Incisive Analog Mixed-signal Verification
Even large, digital designs include an increasing amount of analog circuitry for interfaces, clocking, conversion, and other functions. Complete SoC verification often includes the requirement for verifying that the digital and analog portions of the circuit both work together with a simulator for mixed analog/digital designs.
Fully compatible with the Incisive® verification platform, Incisive AMS is a single-engine, analog/mixed-signal simulator based on production-proven, high-performance core simulation technologies. It is a special configuration of Virtuoso® AMS Designer that allows you to utilize your existing Incisive Simulator license. Incisive AMS facilitates verification of the entire design, from conceptualization to physical realization leveraging tools like, Virtuoso Schematic Editor,Virtuoso Analog Design Environment,Virtuoso Spectre® Circuit Simulator, Virtuoso Spectre RF Simulation Option, and Assura™ physical verification. In addition, it implements standard Verilog®-AMS and VHDL-AMS design languages, allowing you to create, simulate, and analyze your most complex mixed-signal SoCs at higher levels of abstractions.
Key benefits
 | Increases productivity through adoption of a top-down design and verification methodology for complex analog/mixed-signal SoC designs | | Reduces the number of design iterations by mixing digital/analog design blocks at multiple levels of abstraction (i.e., behavioral or device level) | | Leverages the availability of IP and training with industry-standard Verilog-AMS and VHDL-AMS languages | | Promotes design reuse and IP exchange by using any combination of netlist formats: Verilog®, SystemVerilog, Verilog-A, VHDL, Verilog-AMS, VHDL-AMS, Virtuoso Spectre Circuit Simulator, and SPICE | | Enables digital and analog designers to speak the same language |
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