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Home > Products > Incisive functional verification > Design tasks > Building an emulation environment
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Building an emulation environment
As designs grow larger and more complex, design teams must work with numerous emerging technologies. Companies designing chips for high-end wireless, multimedia, and networking applications face large gate-counts, extremely long simulation runtimes, and complex protocols that require many verification cycles to validate. The Cadence® Incisive® Palladium® series and Xtreme® series of accelerators/emulators helps address these challenges and accelerate time-to-market for leading-edge products.
In addition to co-simulation and simulation acceleration, Palladium and Xtreme systems can be used in-circuit to emulate a chip or system in its real environment, prior to working silicon being available. Cadence has turnkey verification environments that can be used to debug designs using stimuli based on real-world data. By combining software applications, hardware emulation, real-world data connections, and stimulus generated by network testers in one complete environment, chips or entire systems can be verified comprehensively and earlier in the development cycle—shaving months from the verification cycle to ensure high-quality first-pass silicon and reliable software.
Cadence offers a complete, high-performance environment for accelerating the verification of third-generation (3G) wireless designs for cellular phones and other wireless communication devices. This environment allows wireless designers who use Incisive acceleration/emulation systems to validate the performance of their complete 3G wireless systems prior to tapeout of their integrated circuit (IC) designs. Cadence also provides designers with leading-edge verification technologies for embedded software content, hardware/software co-verification, integration of IP (RISC and DSP) cores and multimedia processing blocks, and compliance with strict wireless standards.
Cadence multimedia verification environments deliver emulation speeds up to 10,000 times faster than register-transfer-level (RTL) software simulation tools. Cadence has developed the tools and expertise to provide simulation/acceleration and in-circuit emulation technology that helps designers develop and verify silicon chips for set-top boxes, high-definition televisions (HDTVs), PC graphics, the multimedia components of 3G wireless products, and various audio products. Cadence multimedia solutions include the Audio/Video SpeedBridge adapter, the SpeedBridge adapter for PCI Express, and the USB Device SpeedBridge adapter.
Cadence offers a complete high-performance environment to accelerate the verification of Ethernet and Gigabit Ethernet products including switches and routers. This enables network equipment designers to test their complete system (including software and hardware) with real-world network traffic early in the development cycle—reducing the verification process from weeks to hours. Cadence networking solutions include the Multi-Ethernet SpeedBridge adapter, the SpeedBridge adapter for PCI/PCI-X, and the SpeedBridge adapter for PCI Express.
Serial ATA (SATA) and Serial SCSI (SAS) are becoming more viable options for the network-attached storage (NAS) and server storage due to their scalability, affordability, and performance. Cadence offers two new products for in-circuit emulation verification in this area: the SATA SpeedBridge adapter and the SAS SpeedBridge adapter. These adapters enable the target designs (such as SoC, consumer products, and network storage) to verify the system completely and efficiently.
Software Verification Environments
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Nearly all electronics products contain significant amounts of software that must also be verified before the product can be released. High-performance emulation allows application-level software to be verified before first silicon is available, accelerating time to market. Palladium systems support most software debugging environments including Motorola/Freescale Metrowerks, Wind River, Texas Instruments Code Composer, Green Hills Probe, ARM Multi-ICE, and ARM RealView. Palladium systems are unique in their ability to provide a comprehensive hardware debugging environment while also supporting a full-speed JTAG interface to software debuggers.
Palladium systems support hard IP with standard IP blocks through the Palladium IP chassis. Each standard IP block is 100x175mm in size and can have up to 1,248 bi-directional signal pins each. Cadence supplies a number of popular IP cores: ARM processor models via ARM Tiles, including connection to ARM software debuggers; downloadable Xilinx Virtex-II FPGAs; and pin-grid arrays for user-mounting of any silicon.
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