Designing today's complex SoCs requires balancing product requirements, resources and schedules. At the same time, each team must overcome the overwhelming data and process challenge of meeting often conflicting requirements for functionality, performance, power, and cost—all while hitting narrow market windows. And management needs visibility into the project at all times, which includes knowing when to shift priorities or resources.
Sound metrics are critical to managing and optimizing the design process from initial architectural design to final tapeout and printed circuit board design. For example, making the macro tradeoffs necessary for IP and package selection requires early estimates of cost, area and timing. As the detailed design takes shape, these same metrics are then updated and continuously checked against a set of constraints that follow the design as it proceeds from RTL to GDSII. Functional verification metrics like coverage and defect discovery rate are key to understanding the quality of the design, and to establishing the confidence necessary to proceed to tapeout. Chip packaging metrics directly influence PCB development, directly impacting test and assembly and product costs.
Metrics-based technologies for SoC and PCB design process management
To help design teams gain control over their projects, Cadence offers an array of technologies that use metrics to direct and manage product design. These services and products include:
- Methodology and Adoption Services: Methodology assessment, assistance, turn-key development, and collaboration create practical solutions for customers. To ensure project predictability, Cadence® Services provides extensive expertise in production-proven methodologies that address a variety of design needs. All methodologies can be adapted, customized, and optimized to specific customer needs.
- Chip Estimation and Implementation: Using IP acquisition and production costs, the architect can create a project plan to achieve profit margin objectives within the required market window. Implementation parameters constrain resulting chips within the economic feasibility bounds, as well as timing, area, and power goals.
- Functional Verification: Natural language documents can be annotated with verification metrics and used to measure progress towards verification closure. Visibility helps mitigate schedule risks due to missing serious bugs or unverified functionality. Changes in the specification are easily propagated through the design process, shortening reaction time.
- Printed Circuit Board: Managing risk is about early visibility of deviations from the plan. Using metrics to measure design, verification, and implementation, the team easily tracks the project and reacts before problems become a crisis.