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Home > Products > Encounter digital IC design
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ENCOUNTER DIGITAL IC DESIGN PLATFORM |  | The Cadence Encounter platform is an integrated RTL-to-GDSII flow for complex and low-power designs at 90nm and below. | |
To release innovative products in narrow market windows, companies need to focus precious engineering resources on where they add the most value—differentiating their designs. The Cadence® Encounter® digital IC design platform offers a full spectrum of technologies for nanometer-scale SoC design, helping both logic design and physical implementation teams achieve high-quality silicon quickly.
Encounter technology is ideal for:
 | Complex designs over 3M placeable instances | | Aggressive low-power designs | | 65nm/45nm designs and other yield-aware designs | | Mixed-signal designs |
As an integrated RTL-to-GDSII design environment, the Encounter platform provides a complete flow—from RTL synthesis and test design through silicon virtual prototyping and partitioning to final timing and manufacturing closure. It delivers the highest quality of silicon (timing, area, and power with wires), accurate verification, signal-integrity—aware routing, and the latest yield and low-power design capabilities that are critical for advanced 65nm designs. With Encounter technology, you can boost your productivity, manage complexity, and get your products to market faster.
Encounter platform products are available in L, XL, and GXL offerings.
Visit the Cadence Designer Network User Community for user contributed technical articles, product reviews, and interactive forums. Visit www.cdnusers.org.
Read Encounter customer success stories and find out how others are succeeding with Encounter technology.
| Encounter digital IC design platform |
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