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Home > Products > Encounter digital IC design > Demos

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Digital IC design demos and webinars

This page contains demonstrations and webinars related to the Encounter digital design platform.

Demonstrations



Necessary and Absolute Signoff Analysis for 65/45nm Design


Webinars



12/06/07Top-down co-design methodology for System-in-Package Design Webinar Series: Rapid prototyping of multi-chip IC packages using a co-design optimization methodology
11/28/07Top-down co-design methodology for System-in-Package Design Webinar Series: Modeling and analysis methodologies of complex System-in-Package designs
11/13/07Archived Webinar: Top-down co-design methodology for System-in-Package Design Webinar Series: Connectivity-driven logical co-design methodology
09/26/07Archived Webinar: New Approach to Logic Design: A Shift in the Paradigm from Design for Test to Design with Test
10/24/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Advanced timing and SI signoff
10/19/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Automatic validation generation and refinement of constraints
10/18/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Higher quality and lower cost of test
10/17/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Advanced floorplanning and design partitioning for big, fast chips
10/12/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Encounter low-power design flow
10/11/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: 65 nm design flow - scale, yield, power
09/26/06Archived Webinar: Cadence Technology on Tour 2006 Demo Webinar Series: Top-down co-design methodology for SiP design
all webinars