Automatic implementation of digital blocks in mixed-signal designsVirtuoso Digital Implementation automates synthesis, place-and-route, and timing closure for small digital components in mixed-signal designs, accelerating digital block implementation while ensuring the highest quality of silicon.  Cadence Virtuoso Digital Implementation Datasheet » |
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Virtuoso® Digital Implementation is a complete synthesis and place-and-route system. It enables small digital block implementation in the context of an advanced analog-driven methodology. Driven by unified design intent and abstraction, Virtuoso Digital Implementation automates synthesis and optimizes place-and-route to accelerate the mixed-signal design process and ensure the highest quality of silicon. Designed to complement the Virtuoso Layout Suite, Virtuoso Digital Implementation facilitates capacity-limited* execution of a complete digital implementation solution, from RTL to GDSII. It integrates with Encounter® RTL Compiler and Encounter Digital Implementation System to enable functionalities such as high-performance synthesis for smaller, faster, low-power chips, and extremely fast, integrated engines for digital block implementation. *Virtuoso Digital Implementation enables an RTL-to-GDSII solution that is limited in capacity. Encounter RTL Compiler is limited to 50k (final mapped) instances or 200k generic instances. Encounter Digital Implementation System is limited to 50k instances. Two Virtuoso Digital Implementation licenses can be combined ("stacked") to double the capacity limits.
Benefits
- Automates implementation for small digital blocks, including synthesis and physical implementation
- Integrates with the Virtuoso platform through unified design intent and abstraction to deliver a complete implementation solution
- Enables First Encounter® silicon virtual prototyping
- Ensures the best quality of silicon for digital logic (speed, area, and power)
- Supports full-timing modeling of mixed-signal blocks with built-in physical optimization for rapid timing convergence
- Supports timing-driven implementation using a common timing engine with a signoff-quality delay calculator
- Significantly reduces the time to design closure
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