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SoC Encounter RTL-to-GDSII System 


Full-chip implementation in a single system

The SoC Encounter System provides fast and flexible feasibility analysis, giving engineers an early, accurate view of whether the most complex designs will meet their targets and be physically realizable. It offers the latest low-power design and yield capabilities and provides a predictable path to design closure.

SoC Encounter RTL-to-GDSII System Datasheet »
15 resources found
 
Title Type Rated
Improving Emulation Throughput for Multi-Project SoC Designs White Paper
Format: .PDF    Date: 26 Oct 2015
White Paper
 2
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Building Energy-Efficient ICs from the Ground Up White Paper
Format: .PDF    Date: 10 Oct 2012
White Paper
 4
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SoC Encounter System Datasheet
Format: .PDF    Date: 15 Jun 2009
Datasheet
 12
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Practical Guide to Low-Power Design - User Experience with CPF
Date: 16 May 2008
eBook
 46
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Timing closure on a 1GHz DSP-processor using RTL Compiler and SoC Encounter
Format: .PDF    Date: 04 Nov 2007
Conference Paper
 6
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Using Cadence Chip Optimizer with SoC Encounter GXL for Design Closure
Format: .PDF (1MB)    Date: 15 Sep 2007
Conference Paper
 0
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Performance Impact from Metal Fill Insertion
Format: .PDF    Date: 15 Sep 2007
Conference Paper
 1
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Techniques for Custom Routing Using Encounter Technology for a 2GHz Microprocessor
Format: .PDF    Date: 15 Sep 2007
Conference Paper
 1
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More Complex Optimization Methodologies to Improve PPA Results in High-Performance Designs
Format: .PDF (1.1MB)    Date: 15 Sep 2007
Conference Paper
 1
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Common Platform Datasheet for Cadence 65nm Low-Power Reference Flow
Format: .PDF    Date: 01 Jul 2007
Datasheet
 5
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Use of the Incremental Technology Database for Design in IC 6.1 and OA 2.2
Format: .PDF    Date: 15 Apr 2007
Conference Paper
 2
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Real Design Challenges of Low-Power Physical Implementation
Format: .PDF (4.3MB)    Date: 15 Apr 2007
Conference Paper
 1
Recommend!
SoC Cost Reduction by Combining FE-BE Optimisation Techniques
Format: .PDF    Date: 15 Apr 2007
Conference Paper
 0
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Using Advanced Low-power Techniques to Mitigate Headaches, an interview
Format: .PDF    Date: 29 Jan 2007
Cadence Article
 0
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Cadence Encounter Digital IC Design Platform Brochure
Format: .PDF    Date: 01 Apr 2005
Brochure
 20
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