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Cadence Quantus QRC Extraction Solution 


3D full-chip parasitic extraction and analysis

Cadence® Quantus™ QRC Extraction Solution is the industry’s fastest, most accurate parasitic extraction tool. Built with massively parallel technology and integrated with a field solver (Quantus FS), the solution delivers up to 5X faster signoff extraction for system-on-chip (SoC) and custom/analog designs. As a single, unified tool, Quantus QRC Extraction Solution supports both cell-level and transistor-level extractions during design implementation and signoff.

The solution is fully certified for the 16nm FinFET process at TSMC. For better and faster design correlation and convergence, Quantus QRC Extraction Solution is seamlessly integrated with both Cadence Encounter® digital implementation and Cadence Virtuoso® custom design platforms. This integration supports in-design signoff methodology.
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As advanced process geometries continue to shrink, parasitic extraction becomes a necessity throughout the design implementation flow and the validation phase. Quantus QRC Extraction Solution supports all designs down to 16nm—it includes full-spectrum, production-proven technologies for all nanometer-scale design styles including SoC, RF, custom/analog, mixed-signal, memory, standard cells, IP, SRAM/bitcell, custom-digital, and thin-film transistor liquid-crystal display (TFT-LCD). In addition, the solution’s field solver, Quantus FS, supports both SoC and custom/analog designs.

New modeling challenges emerge at 16nm. For example, the introduction of FinFET 3D device structures bring more complex parameters for parasitic capacitance and resistance. These new challenges require the highest level of accuracy in signoff extraction. Quantus QRC Extraction Solution addresses these challenges with its robust modeling infrastructure, which delivers the highest accuracy models and produces the smallest netlist to enable faster simulation and characterization runtimes.

Key Features and Benefits
  • Market’s first massively parallel extraction tool that can scale to utilize up to hundreds of CPUs
  • Accelerates design signoff by providing up to 5X better performance for single and multi-corner extraction over competing solutions
  • Provides up to 5X better performance on a single machine or distributed across multiple CPUs over a large network
  • Features integrated random-walk field solver called Quantus FS
  • Delivers best-in-class 16nm functionality to support FinFET/FDSOI designs
    • Best-in-class accuracy and performance for standard cells, IP, bitcell/SRAM characterization
    • Smallest netlist for all designs
    • Fastest post-layout simulation and characterization runtimes, ~2.5X better than competitive products
    • Faster design convergence in Virtuoso platform using Cgs flow
  • Delivers further performance improvement of up to 3X with automated incremental extraction to reduce design closure turnaround time with Cadence’s Encounter Digital Implementation System and Tempus™ Timing Signoff Solution
  • Provides inductance extraction for SoC digital designs to analyze CLK nets, especially at 28nm and below
  • Features industry-leading functionality such as substrate noise analysis, substrate noise analysis for 3D-IC, inductance extraction, and netlist reduction to support all custom/analog designs
  • Provides unmatched support for PowerMOSFET design extraction with its unique and differentiated meshing features and tightly integrated solution with Virtuoso Power System
  • Supports 3D-IC (TSV) and is fully certified at TSMC