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Cadence QRC Extraction 

3D full-chip parasitic extraction and analysis

The industry’s fastest, most accurate 3D full-chip parasitic extractor, delivering in-design and signoff extraction. It supports both transistor-level and cell-level extractions during design implementation and signoff, and it integrates seamlessly with both Cadence Virtuoso® custom design and Cadence Encounter® digital implementation platforms. This tight integration ensures ease of use, enables rapid analysis to accelerate design closure, and provides better and faster convergence by using the same engine during implementation and signoff.

Cadence QRC Extraction Datasheet »

As advanced process geometries continue to shrink, parasitic extraction becomes a necessity throughout the design implementation flow and the validation phase. Cadence QRC Extraction is an integrated extraction solution for design imple¬mentation and validation at 90nm and below. It includes full-spectrum, production-proven technologies for all nanometer-scale design styles including RF, analog, cell, mixed-signal, custom-digital, and thin-film transistor liquid-crystal display (TFT-LCD). It offers advanced capabil¬ities such as multi-mode/multi-corner (MMMC) extraction, RLCK extraction, advanced process modeling, signoff ECO, substrate analysis, statistical extraction, distributed processing, netlist reduction, DFM effects support, and substrate parasitics extraction, and it includes an integrated, foundry-qualified field solver (QRC-FS).

  • Better, faster, and predictable convergence
  • Productivity and time to market
  • Seamless integration with custom design, digital implementation, and signoff tools
  • Support for all advanced node functionality required at 28/20nm