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Digital Implementation
Cadence® digital implementation technology eliminates iterations without sacrificing design quality by addressing timing sensitivity, leakage power, and yield variation from the start.
Design planning
To create a design layout that fulfills the often-conflicting objectives of performance, power, and cost, engineers must perform comprehensive physical design space exploration and feasibility analysis up front. And with the complexity and size of today’s designs, engineers need a system with the capacity to handle 100M instances and more.
Cadence GigaFlex technology adapts to growing capacity requirements while also retaining the relevant timing, placement, and congestion information to accurately evaluate and analyze complex giga-scale designs. Our giga-scale prototyping foundation flow allows you to implement a silicon virtual prototyping methodology to perform the planning and analysis that ensures a smooth handoff to the physical implementation flow. It also includes the latest low-power design and yield enhancement capabilities to support advanced node designs.
First Encounter Design Exploration and Prototyping
Enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.
Learn more
»
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
Hierarchical design
Achieving rapid design convergence in large, complex chips requires greater capacity, accuracy, and automation than what conventionally rigid hierarchical design flows can provide. Cadence GigaFlex technology is adaptive. It enables precise models to accommodate growing capacity requirements while also retaining the relevant logical and physical information required for each stage of the design.
Our patented FlexModels provide up to 90% netlist compression and an optimized interface for accurate design exploration and planning. FlexILMs retain interface logic for block-level partitions and enable concurrent top- and block-level implementation. FlexViews enable late-stage hierarchical closure by optimizing top-level paths together with inter-partition paths that are timing critical. These technologies ensure fewer iterations and significantly shorter turnaround time. And with unified timing and extraction engines across an integrated flow, you achieve predictable design closure and convergence.
First Encounter Design Exploration and Prototyping
Enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.
Learn more
»
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
NanoRoute Advanced Digital Router
The industry-leading unified routing and interconnect optimization solution that helps designers quickly achieve concurrent timing, area, signal integrity, and manufacturability convergence during digital implementation.
Learn more
»
Block implementation
The Encounter Digital Implementation System block-closure flow offers a seamless continuation from the design exploration stage. Providing functionality from placement to multi-mode/multi-corner post-route closure with signal integrity analysis, it ensures design convergence to get your design from a virtual prototype to a signoff-ready GDSII database.
Our block-closure flow is powered by the latest power, performance, and area (PPA) optimization algorithms. These include our new clock design technology―clock concurrent optimization (CCOpt)―and our new highly scalable GigaOpt physical optimization engine. CCOpt combines clock tree synthesis and physical design optimization in a unified step to offer superior timing closure and productivity improvements. GigaOpt and CCOpt uniquely combine to provide an efficient, physically aware implementation methodology that delivers better quality of results and the best PPA for high-performance microprocessor-based designs.
First Encounter Design Exploration and Prototyping
Enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.
Learn more
»
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
NanoRoute Advanced Digital Router
The industry-leading unified routing and interconnect optimization solution that helps designers quickly achieve concurrent timing, area, signal integrity, and manufacturability convergence during digital implementation.
Learn more
»
Low-power implementation
Encounter Digital Implementation System is an integral part of the holistic Cadence Low-Power Solution, helping you meet aggressive power specifications without compromising timing and area objectives. It leverages unified design intent from the production-proven Common Power Format (CPF) to drive advanced low-power design, optimization, and analysis automatically throughout the flow. Encounter Digital Implementation System supports all major low-power design techniques including power shutoff (PSO), multiple supply voltages (MSV), dynamic voltage and frequency scaling (DVFS), substrate biasing, and more.
First Encounter Design Exploration and Prototyping
Enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.
Learn more
»
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
Encounter Timing System
Offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.
Learn more
»
Encounter Power System
Enables accurate and high-capacity power analysis, helping designers debug and verify that power and IR drop constraints are met across multimillion-gate designs and multiple die—with significant gains in productivity.
Learn more
»
Advanced node design
Faster design convergence at 40nm down to 20nm requires fully integrated and comprehensive design-for-manufacturing (DFM) capabilities. It also requires more complex timing models to handle larger designs. Encounter Digital Implementation (EDI) System’s advanced node design technology prevents and corrects harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely correlated with foundry process simulation), EDI System guides design implementation, minimizes risk up front, and prevents unexpected design re-spins and late-stage iterations.
EDI System also addresses 20nm double-patterning process requirements through a comprehensive physical implementation methodology spanning design exploration to placement, optimization, routing, and signoff. This correct-by-construction approach to advanced node design ensures faster turnaround time in meeting performance, power, and reliability targets while yielding high-quality results in silicon.
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
NanoRoute Advanced Digital Router
The industry-leading unified routing and interconnect optimization solution that helps designers quickly achieve concurrent timing, area, signal integrity, and manufacturability convergence during digital implementation.
Learn more
»
Encounter Timing System
Offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.
Learn more
»
Mixed-signal design
As complex analog functionality and larger amounts of digital logic are integrated in the same die, design teams require consistent and efficient implementation methodologies that maintain both the integrity of mixed-signal design intent and database coherence―across analog and digital domains―at all times, from floorplanning through physical assembly.
Cadence mixed-signal implementation technology offers comprehensive, interoperable digital and analog implementation, optimization, and verification tools and methodologies. It ensures that unified design and verification constraints are carried out throughout the entire flow. Unique design abstraction in an analog/digital co-design environment enables bi-directional management of physical, electrical, and power specifications. These integrated technologies enable fast, accurate, and advanced modeling, signoff analysis, and pre- and post-mask engineering change orders that boost productivity, predictability, and silicon quality.
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
Virtuoso Digital Implementation
A complete and automatic synthesis/place-and-route system that enables capacity-limited block implementation for small digital components in the context of an advanced analog-driven mixed-signal design.
Learn more
»
3D-IC design
3D-ICs with through-silicon vias (TSVs) pack a great deal of functionality into small form factors while improving performance and reducing costs. 3D-IC packages also accommodate multiple heterogeneous die, such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS). And since 3D-ICs support such a wide variety of process nodes―such as 28nm for high-speed logic and 130nm for analog―you have the flexibility to place in a single package all of the functionality you want without having to make an expensive move to a new process node.
Cadence stacked-die technology offers an automated 3D-IC/TSV design methodology integrated with implementation, extraction, and analysis tools. It captures design intent up front so you can pass design intent seamlessly throughout the flow. It then abstracts physical information to help you optimize 3D floorplanning and placement across multiple heterogeneous die, IC package, and board. Tight links to Cadence custom IC and system-in-package design environments allow for continuous convergence, ensuring a manufacturable packaging solution. Robust thermal analysis and power management capabilities support design closure; TSVs and the use of silicon interposers support both intermediate and long-term design needs.
3D-IC white paper
»
3D-IC technical paper
»
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
Design closure
The performance requirements and scale of today's digital designs pose challenges to achieving aggressive power, performance, and area goals, and they impact runtime. Encounter Digital Implementation System’s design closure technology is a fully integrated part of the Cadence digital end-to-end flow. It offers a full set of physical implementation technologies―from design exploration to signoff for both flat and hierarchical designs―powered by an end-to-end multi-CPU backplane. In a single environment, you can achieve the best power, performance, and area results for your high-performance/low-power, giga-scale, and mixed-signal designs using either mainstream or advanced process technologies.
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
Signoff analysis
Successful digital chip design hinges on accurate and consistent signoff analysis. With Cadence signoff analysis technology, you can perform all of your electrical verification tasks in an integrated, easy-to-use environment. This includes front-end to back-end design handoff, signoff-driven implementation, and final signoff convergence. Cadence technology analyzes timing with variation and noise, power consumption, IR drop, electromigration, and thermal characteristics―with high precision. It also leverages electrical abstraction models and a scalable multi-CPU infrastructure to accelerate signoff on large designs. And with our multi-dimensional root-cause analysis capability, you can shave weeks off of tapeout schedules and prevent silicon failures to further improve your productivity and profitability.
Cadence Physical Verification System
The premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
Learn more
»
Encounter Timing System
Offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.
Learn more
»
Encounter Power System
Enables accurate and high-capacity power analysis, helping designers debug and verify that power and IR drop constraints are met across multimillion-gate designs and multiple die—with significant gains in productivity.
Learn more
»
Cadence QRC Extraction
The industry’s fastest, most accurate 3D full-chip parasitic extractor, delivering in-design and signoff extraction.
Learn more
»
Manufacturability signoff
At today’s advanced nodes, digital implementation software must account for the challenges of smaller transistors and wires, as well as the data capacity and complexity challenges of denser and more complex chips. Cadence solutions for manufacturability take the knowledge of creating the mask and how the chip is going to be manufactured, and bring them back into the design phase. This helps designers compensate for physical effects at nanometer geometries while providing a reliable way to achieve manufacturing signoff before tapeout.
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence Physical Verification System
The premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
Cadence CMP Predictor
Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.
Learn more
»
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP for SoC designs.
Learn more
»
Cadence Chip Optimizer
Uses a 3D space-based approach that models, analyzes, and optimizes layout based on electrical constraints, manufacturing rules, and objectives.
Learn more
»
Cadence CMP Predictor
Optimizes design performance through model-based intelligent metal fill and hotspot detection and correction.
Learn more
»
Cadence Litho Electrical Analyzer
Extracts device and interconnect electrical behavior from contours. Detects and repairs timing and leakage hotspots due to systematic variations.
Learn more
»
Cadence Litho Physical Analyzer
Detects and corrects lithography hotspots. Uses a model-based technology to predict silicon contours quickly and accurately. Improves parametric yield and chip performance.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Cadence Physical Verification System
The premier Cadence signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking.
Learn more
»
Cadence QRC Extraction
The industry’s fastest, most accurate 3D full-chip parasitic extractor, delivering in-design and signoff extraction.
Learn more
»
Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
Learn more
»
Encounter Power System
Enables accurate and high-capacity power analysis, helping designers debug and verify that power and IR drop constraints are met across multimillion-gate designs and multiple die—with significant gains in productivity.
Learn more
»
Encounter Timing System
Offers silicon-accurate timing signoff and signal integrity analysis that ensures operational chips after tapeout.
Learn more
»
First Encounter Design Exploration and Prototyping
Enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.
Learn more
»
NanoRoute Advanced Digital Router
The industry-leading unified routing and interconnect optimization solution that helps designers quickly achieve concurrent timing, area, signal integrity, and manufacturability convergence during digital implementation.
Learn more
»
Virtuoso Digital Implementation
A complete and automatic synthesis/place-and-route system that enables capacity-limited block implementation for small digital components in the context of an advanced analog-driven mixed-signal design.
Learn more
»
Content Query Web Part [2]
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A Call to Action: How 20nm Will Change IC design White Paper
Clock Concurrent Optimization Technical Paper
Building Energy-Efficient ICs from the Ground Up White Paper
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