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Digital Implementation 

Cadence® digital implementation technology eliminates iterations without sacrificing design quality by addressing timing sensitivity, leakage power, and yield variation from the start.

Design planning
To create a design layout that fulfills the often-conflicting objectives of performance, power, and cost, engineers must perform comprehensive physical design space exploration and feasibility analysis up front. And with the complexity and size of today’s designs, engineers need a system with the capacity to handle 100M instances and more.

Cadence GigaFlex technology adapts to growing capacity requirements while also retaining the relevant timing, placement, and congestion information to accurately evaluate and analyze complex giga-scale designs. Our giga-scale prototyping foundation flow allows you to implement a silicon virtual prototyping methodology to perform the planning and analysis that ensures a smooth handoff to the physical implementation flow. It also includes the latest low-power design and yield enhancement capabilities to support advanced node designs.

Innovus Implementation System
Cadence® Innovus™ Implementation System is a physical implementation tool that delivers typically 10-20% production-proven power, performance, and area (PPA) advantages along with up to 10X turnaround time (TAT) gain in advanced 16/14/10nm FinFET designs as well as at established process nodes.
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First Encounter Design Exploration and Prototyping
Enables quick full-chip virtual prototyping to accurately capture downstream physical/electrical impacts at the beginning of the design cycle. Its unique partitioning and budgeting capabilities combined with GigaFlex Abstraction Technology makes hierarchical implementation easier and faster for giga-scale, high-speed designs.
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Encounter Digital Implementation System
Provides the most effective methodology to maximize performance, and minimize power and area for high-performance, giga-scale designs.
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